Testbenches have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore, that you have confidence your testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.
To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
ModelSim provides an Integrated Debug Environment that facilitates efficient design debug for SoC and FPGA based designs. This GUI has continuously evolved to include new windows and support for new languages. This application note aims to give an introduction to the ModelSim 6.0 debug environment. This environment is trilingual supporting designs based on VHDL, Verilog (all standards including SystemVerilog, Verilog 2001 and Verilog 1995), and SystemC. Subsequent releases of ModelSim will enable even more debug capabilities supporting higher levels of abstractions for verification and modeling in SystemVerilog and SystemC. In ModelSim 6.0, the GUI has been enhanced and is based on Multiple Document Interface (MDI) layout standard. In addition, the debug windows have been re-organized in such a way as to display design data and simulation results in an intuitive manner.
This document introduces SystemC verification with ModelSim, starting with setting up the simulation environment, and followed by a discussion of the use model. Information on using SystemC across Verilog and VHDL boundaries is also presented. A sample design is used to illustrate the current capabilities in ModelSim.
SystemVerilog (SV) is the next generation of the popular Verilog language. As an extension to the IEEE 1364-2001 Verilog standard (referred to hereafter as Verilog) SV has been carefully designed to be 100 percent backward compatible. Under Accellera (the standards body responsible for defining SystemVerilog ), SV has evolved in recent years. Version 3.0 was approved by the Accellera board at the Design Automation Conference (DAC) in June of 2002. This version concentrated on synthesizable design enhancements. Version 3.1 was approved by the Accellera board in June 2003 and added many enhancements aimed at the verification arena. At DAC 2004, an even more enhanced version of SystemVerilog (v3.1a) was officially handed over to the IEEE for standardization. That work is expected to take about a year. ModelSim® 6.0 builds on the SV features added in ModelSim 5.8 and adds many exciting new features,some of which we will discuss here.
C and C++ languages have an important role to play in ASIC design, and using these languages can significantly increase designer productivity. However, C and C++ cannot be used entirely alone; they must work together with conventional HDLs (VHDL and Verilog), to create a mixed HDL and C/C++ environment. The key to success when employing a mixed environment in ASIC design is to choose and use the language that offers the most effective abstraction level for the task at hand.
This document describes the use of the open source tool, Valgrind, to detect and track down the memory usage errors in user-created C/C++ source files in ModelSim simulation. The Valgrind tool is limited to use with x86/linux based platforms.
This application note discusses how to use Vera® and ModelSim® together. It assumes you are comfortable working with both Vera and ModelSim. Please keep in mind that Synopsys® provides the most complete reference for using ModelSim with Vera.
Support for the Verilog-2001 standard (IEEE 1364-2001) in Model Technology’s ModelSim® simulator was rolled out over four different releases. Initial support began in March of 2001 with the release of version 5.5. With the latest release of ModelSim, version 5.8, Model Technology is the first EDA Company to complete its implementation of the entire Verilog-2001 standard. The intent of this article is not to exhaustively list all the new features in Verilog-2001 nor to regurgitate the LRM, but rather highlight and illustrate some of the more important features in the new Verilog standard.
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