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 Your Resource for Design & Verification Information October 31, 2004 
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Spotlight - DAC 2004

ModelSim at the 41st Design Automation Conference, 2004
Mentor Graphic Booth #626, San Diego, CA

Come view the leading performance and complete verification environment, ModelSim. As designs continue to grow in size and complexity, there is a greater need for advanced verification solutions. New languages and methodologies have emerged to address the ever growing verification gap. Take a look at how ModelSim supports all major standards including SystemVerilog, PSL, and SystemC. ModelSim's Verification Environment enables support for methodologies in areas of assertions, and coverage-driven verification combined with the best integrated debugging environment in the industry.

Stop by and find out how ModelSim will help you solve your current and future design, verification and debug needs.

All sessions will be held on site at the DAC 2004 conference:
San Diego Convention Center. Register today!

I won't be able to attend DAC, please have a local representative contact me.

Release Information 
ModelSim 6.0
Seamless FPGA Download

Developed in partnership with Xilinx for the Virtex-II Pro and Virtex-4, Seamless FPGA provides an enhanced PowerPC model which connects the XRAY software debugger with a hardware design running in ModelSim to speed design completion.

 Download free evaluation software! Find out more.
Technical Resource Center

Check out all the exciting offers ModelSim has to offer through our technical resource center.

  • Register today to gain unlimited access to our in-depth technical documents such as application notes, white papers, product documentation and release notes.
Standards Corner 

IEEE Consolidates Verilog Standards in One Working Group

The IEEE Standards Association has approved a plan to consolidate the Verilog P1364 project under the SystemVerilog Working Group (SV WG) that manages P1800. As part of this consolidation, the P1364 project was changed to Entity balloting – one company, one vote – to match that of P1800.

The short-term goal of the SV WG is to review the donated Accellera SystemVerilog 3.1a specification for needed cleanup, clarifications and corrections to errata. No enhancements will be considered in this version. The SV WG has collected and cataloged issues to start this process. The list of issues is open for public inspection. Public access to this database is offered with the username guest and password guest. Similarly, P1364 scope has been set to likewise address needed cleanup, clarifications and errata to the 1364-2001 specification without the introduction of extensions of modifications.
Dennis Brophy, Director of Strategic Business Development
The long-term goal is to maintain proper alignment and coherence between IEEE SystemVerilog and Verilog language with the possible merging of the two specifications into one. To facilitate this process, the SV WG has already begun to create a single errata committee and a single interface committee. For those who may have worried that there may have been conflicts in usage between SystemVerilog and Verilog, you should rest assured there will be no conflicts. One working group will be able to resolve any such inconsistencies.
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ModelSim Workshops

PSL Workshop          Kanata, Ontario Canada
November 09, 2004

SystemVerilog Workshop                  St. Laurent, Quebec Canada
November 10, 2004

ModelSim and 0-In Assertions Seminars

Irvine, CA
November 08, 2004

Austin, TX
November 09, 2004

Tempe, AZ
November 10, 2004

San Jose, CA
November 15, 2004

Westford, MA
November 16, 2004

Kanata, Ontario Canada
November 17, 2004

Bloomington, MN
November 18, 2004

Electronica

Munich, Germany   November 9 -12, 2004

EDA Tech Forum

Dallas, Texas
November 17, 2004

User2User 2005

Call for participation is now open!

ModelSim Training

PSL Assertion Based Verification with ModelSim

San Jose, CA
January 06, 2005