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 Your Resource for Design Tools October 31, 2003 

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Spotlight
Model Technology announces ModelSim® 5.8 
A Complete System-level Verification and Debugging Environment for Complex ASIC and SoC designs. [more...]

North American Seminar: Advanced Verification and Debugging with ModelSim
To learn more, join us for a half-day technical seminar focusing on new verification technologies including, C/System C, PSL, Assertions, Verilog 2001, System Verilog and more to help you be more productive.
Register for the seminar today!

Release Information
Download Latest Release ModelSim 5.7g
Technical Publications
Partner News
'Structured ASIC': The trend in design starts in FPGA and ASICs shows over the last years a steady increase of FPGA design starts and a decreasing trend in ASICs. The reasoning is that with the most advanced technologies the manufacturing cost of ASICs is growing out of proportion. Therefore only designs with appropriate volume or performance requirements are suited for Standard-Cell ASICs nowadays. 

Leading ASIC vendors (e.g. LSI, NEC, Fujitsu) released products (e.g. RapidChip(TM), ISSP(TM), AccelArray(TM)) addressing the changing market requirements. 'Structured ASICs' combining the advantages of Standard-Cell ASICs together with the ones of FPGAs. Standard-Cell ASIC advantages are high complexity, high density and high performance. FPGAs are known for short time to market, flexibility, low NRE costs, easy to use and well suited for low to midrange quantity designs. Our longstanding relationships with these Silicon Vendor Partners enables our customers today to simulate their 'structured ASIC' with ModelSim.

ModelSim is a highly recognized simulator throughout the silicon vendor community (ASIC, FPGA & 3rd Party library suppliers). Model Technology's Silicon Vendor Partners program works with 30 silicon vendors worldwide. This assure the continuous support of the newest ASIC - FPGA technologies through sign off / qualified VHDL and Verilog libraries. Currently 240 VITAL and 270 Verilog libraries are sign off / qualified for ModelSim.
Standards Corner
Free Assertion Monitors

In the past decade, design and verification teams have begun to see the value of embedded checkers and assertions in their HDL code. Numerous papers have been presented at design automation and verification conferences that show the success of checkers to find bugs in designs that where were already thought to be relatively bug free.

Are you using checkers and assertion monitors yet? Through the generosity of those verification trailblazers, advanced verification assertion monitors have been donated to Accellera and are being incorporated into a proposed Open Verification Library Assertion Monitor Reference Manual. 

A review copy of this manual is available for download. In addition to the text which defines the assertion monitors, there are proposed implementations in Verilog and VHDL that you can use in Appendix A & B. These assertion monitors work with all Verilog and VHDL simulators and no fee is required use them. You can also download the proposed Accellera VHDL or Verilog assertion monitors from model.com. The Accellera OVL team seeks feedback on them. Send  a email to OVL if you have comments, feedback or suggestions on improvements or additions.

Dennis Brophy, Director of Strategic Business Development
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ModelSim Seminars
System Verilog Now!

Ottawa, Canada 
November 12, 2003

Please Register!

X-Fest

Offered in 37 locations across North America, X-Fest runs from early October through mid-December.

Enroll now since space is limited.

Israel Solution Expos 

Herzliya, Israel          November 4, 2003 

Altera SOPC World

Around Europe            Oct. 30 - Nov. 20, 2003

ModelSim  Training

Expert VHDL  Verification                San Jose, CA       November 10, 2003 

HDL Simulation Using ModelSim              Marlborough, MA     November 11, 2003  

ModelSim Advanced Debugging                  Marlborough, MA   November 12, 2003

Comprehensive VHDL Chicago, IL      November 17, 2003