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 Your Resource for Design & Verification Information September 27, 2004 
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Spotlight 
SystemVerilog for Verification
Come See it in Action!

Please join us for drinks and hors d'oeuvres as Cliff introduces powerful SystemVerilog 3.1a features to enhance verification productivity for use TODAY. In addition, see ModelSim in action through a comprehensive demonstration of SystermVerilog 3.1a features available NOW.

Join us in one of  these cities and you could win!

Boston, October 12th
Minneapolis, October 13th
Austin, October 14th

RSVP and you could win.

When you register and attend you will be automatically entered to win a Apple iPod mini that will be handed out at the event.
Release Information 
ModelSim 6.0
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Partner News
Doulos announcing training class: 'SystemVerilog Using ModelSim'
 
SystemVerilog is a significant new language, based on the widely used and industry-standard Verilog® hardware description language. The SystemVerilog extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in architecture and system design.

'SystemVerilog Using ModelSim' is based on the current Accellera SystemVerilog standard 3.1a. Through a carefully designed combination of tutorials and workshops focusing on the language features supported by ModelSim, delegates will learn how to take advantage of the language, methodology and tool specifics to improve their designs and verification. The course will be enable delegates to start using SystemVerilog effectively with ModelSim immediately after the training. 'SystemVerilog Using ModelSim' is a Doulos partner course developed and marketed in co-operation with Mentor Graphics.

'SystemVerilog Using ModelSim' is aimed at hardware and verification engineers who wish to start using SystemVerilog with the ModelSim simulator. The training course is also suitable for anyone requiring a detailed hands-on technical overview of how to use SystemVerilog today and how its application can enhance productivity in the areas of design and verification.
Standards Corner 

SystemVerilog DPI – Ready for Use

New in ModelSim 6.0 is support for the SystemVerilog Direct Programming Interface (DPI).  The SystemVerilog DPI is an advanced and powerful interface between SystemVerilog and a foreign programming language like C or C++.  DPI allows SystemVerilog to call foreign language functions and foreign language functions to call SystemVerilog functions.  This is all done without the overhead and knowledge of Verilog’s PLI or VPI layer.  This makes DPI a more efficient method to connect C/C++ functions with SystemVerilog since the interface layer is no longer required.

Information on the DPI can be found in the SystemVerilog 3.1a specification, which is available for free download from Accellera.  Project VeriPage also has a new online tutorial to teach you more about the use of DPI and how to connect C/C++ code with SystemVerilog code.  The tutorial demystifies DPI and makes it easy to see the power and value of this new foreign language connection method specified in the SystemVerilog standard.
Dennis Brophy, Director of Strategic Business Development
If you are a ModelSim Verilog user, and have not yet downloaded ModelSim 6.0, you can now do so to use DPI.  ModelSim 6.0 is now the default production release and has implemented the SystemVerilog DPI.  If you are not yet a ModelSim Verilog user and would like to learn more about SystemVerilog DPI and gain some firsthand experience with it, you can always download an evaluation copy of ModelSim 6.0 to evaluate SystemVerilog and the SystemVerilog DPI yourself.
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ModelSim Seminars

ModelSim (Hi Speed) Seminar

Longmont, Colorado
October 8, 2004

Longmont, Colorado
November 4, 2004

ModelSim 6.0 Verification Environment Seminar

St.Petersburg, Florida
October 20, 2004

ModelSim Workshop

Orlando, Florida
October 26, 2004

Faster Completion Of Your Xilinx Embedded Design

Registration and more details available here.

International EDA Tech Forum

North America & Europe

Click here for more details

User2User 2005

Visit here for details, topic ideas and to submit your abstract online.

Call for Papers - Deadline: October 29, 2004

ModelSim Training

HDL Simulation Using ModelSim

Longmont, Colorado    October 6, 2004

ModelSim Advanced Debugging

Longmont, Colorado    October 7, 2004

PSL Assertion Based Verification with ModelSim

Dallas, Texas        October 21, 2004

NEW! SystemVerilog NOW

SystemVerilog NOW is not just another language syntax course, but a design and methodology learning experience where you will walk away with skills you can use at work.

San Jose, CA  December 1,2004