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 Your Resource for Design Tools September 29, 2003 

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Spotlight
Mentor Graphics EDA Tech Forum

Preview ModelSim's latest release with advanced verification and debugging functionality. 

Additional Highlights:

  • Keynotes by industry leaders from Gartner Group, IBM, and more.
  • Cutting edge technical sessions and technology fair focusing on real design issues for Design-to-Silicon.
  • Functional Verification, FPGA Design, PCB Design and Design-for-Test.
  • A product showcase featuring the latest innovations that will take your EDA design to the next level.
Register for the 2003 EDA Tech Forum!

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Release Information
Download Latest Release ModelSim 5.7f
Technical Publications
Partner News
The Model Technology Silicon Vendor Partner Program covers the areas of ASIC, FPGA, and COT (Customer Owned Tools). All of these areas are unique when it comes to delivering design flows and libraries. ASIC and FPGA vendors want to ensure 'first pass success', therefore they need to define and qualify vendor specific design flows. In addition, ASIC and FPGA vendors deliver sign-off libraries for qualified EDA tools. In contrast with a COT environment, it is up to the each company using foundry processes to define their own design flow and create their own library view for the different front-end EDA tools.

This distinction in methodology created the business of 3rd-party library supplier (e.g. Artisan, Virtual Silicon and others). They partner with foundries (TSMC, UMC, Chartered and others) and EDA vendors. This enables library suppliers to deliver qualified front-end libraries for the different foundry processes.

Model Technology has a longstanding relationship with 3rd-party library suppliers. They are using ModelSim to run their regression suites with VHDL and Verilog simulation libraries and supply our customers with those qualified libraries. Currently, they provide about 50+ libraries for ModelSim covering processes from 0.25 micron down to 90nm.
Standards Corner
The latest news from the VHDL-200x working group is the approval of an advisory vote to use Accellera's PSL as the foundation for VHDL's assertion-based verification (ABV) capabilities. The advisory vote did take notice that Accellera has directed the Formal Verification Technical Committee (FVTC) and SystemVerilog groups to make PSL and SystemVerilog Assertions compatible. As the VHDL-200x assertions team plans on incorporating PSL by reference, this future version of PSL will be the version incorporated. 
PSL provides the ability to define properties that can be proven by formal methods as well as checked during simulation. Some property expression capabilities are poorly suited for simulation as time branching can be implied. Therefore, PSL identifies a Simple Subset that ensures monotonically increasing time. The assertions team will identify language changes necessary to support the Simple Subset of PSL natively (without the need for meta comments/pragmas) in VHDL.
Stephen Bailey, Technical Marketing Engineer
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ModelSim Seminars
System Verilog Now!

Austin, TX 
October 8, 2003

Santa Clara, CA 
October 22, 2003


Boston, MA 
October 29, 2003

Ottawa, Canada 
November 12, 2003

Please Register!

X-Fest

Offered in 37 locations across North America, X-Fest runs from early October through mid-December.

Enroll now since space is limited.

Solution Expos in Europe

Kista,  Sweden          October 2-3, 2003 

Reading, UK     October 8, 2003

Sonthofen,Germany       October 9-10, 2003

ModelSim  Training

Comprehensive VHDL  San Jose, California October 20, 2003

HDL Simulation Using ModelSim              San Jose, California     October 14, 2003  

ModelSim Advanced Debugging              San Jose, California    October 15, 2003

Expert VHDL Verification             San Jose, CA       November 10, 2003