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 Your Resource for Design & Verification Information August 27, 2004 
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Spotlight  - Announcing ModelSim 6.0
Presenting ModelSim 6.0

Productivity is the goal and 6.0 delivers across the board in its support for Assertion-Based verification, functional coverage, higher levels of abstraction and more concise design descriptions with SystemVerilog to GUI enhancements that improve the analysis and debug of designs.  Learn More >>

Features
  • Assertion-Based Verification with PSL support
  • Tri-lingual simulator with VHDL, Verilog and SystemC
  • SystemVerilog support for Design
 Benefits
  • Increases Verification and debug productivity
  • One environment to work with any language
  • Next generation Verilog with new verification and test capabilities
Release Information 
ModelSim 6.0
Technical Resources 

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  • FREE ModelSim Product Information CD
Standards Corner 

 IEEE Creates One Verilog Working Group

The recent months have seen a great deal of discussion on the evolution and enhancement of the Verilog hardware description language within the IEEE.  When Accellera completed and approved the SystemVerilog 3.1a language reference manual prior to DAC 2004, it opened a path within the IEEE that had strong market relevance and corporate participation in Verilog’s evolution.  In response to this, the IEEE Corporate Advisory Group and the Design Automation Standards Committee established the SystemVerilog Working Group to work on the two Verilog projects: P1800 and P1364.

Dennis Brophy, Director of Strategic Business Development
With recent IEEE-SA board approval, these two projects are now entity-based activities within a single working group.  There is no worry that two projects would split to create two standards for the Verilog language.  As you will find in ModelSim 6.0, the implementation of SystemVerilog is a natural extension to classic Verilog-1364.  Just as it is natural there, it is natural for the two projects to be in one working group.  And in one working group, there is no risk to the introduction of incompatibilities.  To see for yourself the power of SystemVerilog, download ModelSim 6.0 to test and use the advances offered in SystemVerilog.
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