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 Your Resource for Design & Verification Information July 28, 2004 
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ModelSim 5.8d
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Partner News
90nm support for ModelSim

Most of the top 10 Silicon Vendors worldwide are offering 90nm technologies to their customers. This means maximum available gates up to 100 million gates, 6 to 10 different metal layers, inverter gate delay of around 11ps (F/O=1), power consumption of a NAND gate of around 2.5nW/MHz/BC with a F/0=1. Overall customers are exposed to a significant amount of more silicon area compared to previous technologies where average design sizes are approximately between 5 to 10 million gates. With the 90nm technologies customer design sizes are between 15 to 30 million gates, not counting the memory. Silicon Vendors are addressing power sensitive or high performance designs by  offering different specialized libraries.

Verification challenges include signal integrity, power consumption, functional verification on RTL level and functional / timing verification on gate level for sign off purpose. To assure sign off quality of VHDL / Verilog libraries, Mentor Graphics ModelSim group works together with all Silicon Vendors worldwide. In respect of the supported 90nm technologies Silicon Vendors tend to favor mainly the support of Verilog libraries. The reason is that Verilog provides a more efficient way to model the library cells. The impact to the user is that they are gaining significant simulation performance and reduced memory footprint compared to VHDL/VITAL. Current VHDL customers are able to maintain their VHDL RTL front-end and still gain the Verilog gate level performance advantages leveraging ModelSim Mixed Language capabilities. ModelSim provides in conjunction with 15 Silicon Vendors mixed sign off design / verification flows (e.g. VHDL RTL - Verilog gates).

Please visit model.com to review the current ModelSim library sign off / support from our worldwide Silicon Vendors.
Standards Corner 

 Accellera Approves PSL 1.1

At DAC this year, Accellera approved the Property Specification Language (PSL) standard version 1.1 as an Accellera design verification standard, and that the organization has begun the IEEE standardization process for PSL with the IEEE Corporate Advisory Group (CAG).

The PSL 1.1 effort focused on refinement of PSL 1.01 and on alignment between PSL and SystemVerilog Assertions (SVA) where possible. In addition to correcting errata discovered in PSL 1.01, PSL 1.1 incorporates new features and user-driven enhancements. The PSL extensions subcommittee focused on common requests from users, including the addition of SystemVerilog flavor, adoption of SVA built-in functions, addition of labels on directives as well as report clauses on certain directives, relaxation of some flavor macros and refinement of operator precedence.
Dennis Brophy, Director of Strategic Business Development
To find out how the capture the functional specifications of logic design—in a way that is non-ambiguous, effective and concise—using the notion of properties and assertions, Accellera has made the PSL 1.1 Language Reference Manual available for free download .
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