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 Your Resource for Design Tools June 30, 2004 
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Spotlight 

ModelSim 5.8d is now available!

  • The Wave window has a new keyboard shortcut 's' to bring the currently active cursor into view. 
  • The Dataflow window can now be used for HDL regions of mixed SystemC designs.
  • Off-line code coverage reporting is now available with the vcover utility.
  • You can now save a specified instance limited to only one level. Before the specified instance and all instances below it were saved.

Didn't make it to DAC and want to find out the latest on Assertions, SystemVerilog, SystemC and Advanced Debugging from ModelSim? Please have a local representative contact me and send me the FREE Scalable Verification mini CD kit. 

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ModelSim 5.8d
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Standards Corner 

 IEEE Approves SystemVerilog

The IEEE Standards Association Board has approved the SystemVerilog standardization project and has numbered it P1800. In a move to unify the Verilog projects, the IEEE Corporate Advisory Group (CAG) and Design Automation Standards Committee (DASC) will also co-sponsor the projects under one working group. 

The IEEE CAG, DASC and Accellera reached an accord that brings harmony to the Verilog standards projects within the IEEE that addresses the interests of industry with entity operation. The IEEE CAG and DASC agreed to place the existing P1364 Verilog project under the same working group to ensure there is one Verilog standard.
Dennis Brophy, Director of Strategic Business Development
After Accellera approved SystemVerilog for transfer to the IEEE CAG there was much written about what this meant to Verilog standardization that left doubt and uncertainty about what would happen in the IEEE. The worst was predicted. The IEEE 40-day comment period allowed the CAG to meet with the DASC to arrange sponsorship of SystemVerilog to meet efficiency in the standardization of SystemVerilog. The conclusion was one Verilog working group with the two projects within it.

The IEEE process has worked and has resulted an outcome that has the acceptance of all. For all users of Verilog, you can now rest assured that there will only be one Verilog. 
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