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April
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| Spotlight
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The Mathworks and Mentor Graphics Win EDN Innovation of the Year Award for Link for ModelSim
The MathWorks® and Mentor Graphics® today announced that The MathWorks software tool Link for
ModelSim® won the EDN Innovation of the Year Award in the EDA: Design Exploration category. This exclusive awards program honors outstanding electronic products, ranging from integrated circuits to test equipment, and the creative engineers who invent them.
We are pleased that The MathWorks Link for
ModelSim co-simulation interface is lauded by our industry peers," said Robert Hum, vice president and general manager, design verification and test division, Mentor
Graphics. "Mentor Graphics and The MathWorks are committed to providing designers with an innovative, efficient tool flow to co-simulate, test and verify mixed-system level design descriptions in MATLAB or Simulink with VHDL and
Verilog." [more...]
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ModelSim Reinstatement Promotion
One of the most cost-effective ways to improve designer productivity at your site is to bring your lapsed ModelSim seats back on current support.
By reinstating support you can upgrade your inactive seats to the most current release and take advantage of the newest functionality. You also get access to all our online
SupportNet
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| Release
Information
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ModelSim
5.8c
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5.8 Technical Notes
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| Partner
News
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ISSP – the right choice for low- to mid-volume ASIC designs at low NRE cost
Up to now, there have been two main approaches to developing high-complexity custom circuits: cell-based or standard cell ASICs (CB-IC) and – within certain limitations – field programmable gate arrays
(FPGAs). CB-ICs are capable of delivering the highest performance for optimal area efficiency and lowest power, but have the drawback of relatively high mask cost. FPGAs have the advantage of being programmable, so that mask costs fall away. This is a benefit during the development and system-test phases, because designs can still be modified without significant extra cost. But the aspects of FPGAs that initially seemed so attractive turn out to have serious downsides: the ability
to
reprogram means higher unit costs, which are caused by a larger area of silicon and a larger and more
expensive package to accommodate the greater number of pins required for reprogram
and higher power consumption. This situation leaves designers with the often difficult choice between the high unit costs of FPGAs and the high mask costs of CB-ICs. This is where the new concept of “structured ASICs” comes into the calculation.
[more...]
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| Standards
Corner
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Mentor Graphics IEEE
Membership
Mentor Graphics recently announced it has joined the
IEEE Standards Association (IEEE-SA) as a corporate member to help shape industrial involvement in the development of standards. In the last few years, the
IEEE-SA has initiated a program to embrace corporate issues in the development of standards that has traditionally been done by consortia. Since IEEE standards for electronic design automation underpin virtually every digital design done today, corporate input should likewise be part of this process.
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| Dennis
Brophy, Director of Strategic Business Development |
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| The IEEE VHDL and Verilog standards offer a solid base for modern design practice with efficient support of design data interoperability. These standards give you implementation choices and innovative technologies you use in your design methodologies. But those standards have failed to keep pace with the changes in design complexity and have failed to address the crisis in verification. With recent industry surveys that show up to 70% of the design process is spent in verification, it is past time that this issue is addressed. Corporate feedback and participation in the IEEE-SA will allow issues like this to be surfaced and resolved with more timely standards and specifications. Mentor Graphics looks forward to its corporate participation in the IEEE-SA and the benefits it will offer you as we speed the development and deployment of crucial electronic design automation standards.
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Advanced Verification with ModelSim 5.8
Seminar
Minneapolis, MN
May 12, 2004
Atlanta,
GA
May 18, 2004
Cleveland, OH
May 19, 2004
Dulles,
VA
May 19, 2004
Houston,
TX
May 25, 2004
Roanoke,
VA
May 27, 2004
For additional locations
visit our website.
Rapid Embedded System
Design & Optimization
Worldwide
April 29 - May 21, 2004
UK & Benelux 2004 Designer Forums
A special event focusing on the technical challenges for EDA whilst designing electronic systems.
Camberley,
England
May 5, 2004
Livingston,
Scotland
May 18, 2004
Dublin,
Ireland
May 20, 2004
Cambridge,
England
June 16, 2004
ModelSim Training
PSL for ModelSim
ModelSim Basic Course Register
Online
ModelSim Advanced
Techniques Register
Online
HDL Simulation Using ModelSim
San
Jose, CA May 11, 2004
ModelSim Advanced Debugging
San
Jose, CA
May 12, 2004
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