| Spotlight
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Safelogic's
Monitor® Adds PSL Support in ModelSim
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The Safelogic Monitor® plug-in for ModelSim allows design and verification teams to exploit the proposed Accellera Property Specification Language (PSL) in ModelSim. Design and verification teams can easily use property or assertion based verification without the need to modify the design. Through the use of ModelSim's Foreign Language Interface (FLI), Safelogic Monitor allows property based simulation of VHDL, Verilog and mixed-HDL designs. The power of properties
combined with graphical error tracing and property coverage in the ModelSim user interface provides an improved RTL design and verification process.
Learn how you can download an evaluation copy of Safelogic Monitor
[more...]
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Download
Latest Release ModelSim 5.7c
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| Technical
Resources
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| Standards
Corner
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SystemVerilog: Discover the Details for Yourself
As a ModelSim user, you are being given an advanced notice and invitation to attend the SystemVerilog workshop at the 40th Design Automation Conference (DAC) in Anaheim, CA. The workshop is free, but seating is limited and registration is required. The workshop will be held on Monday, June 2nd in room 304 at the Anaheim Convention Center. Doug Warmke, Director of Engineering at Model Technology will be one of the presenters. His topic is the SystemVerilog C Interface and APIs.
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| Dennis
Brophy, Director of Strategic Business Development |
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Register
today to attend! SystemVerilog, a set of extensions to the IEEE 1364-2001 standard, enhances Verilog for next generation design and verification. The workshop is structured in several parts to allow you to best schedule your time so you can also take advantage of the free tradeshow access. The four main parts of the workshop include (1) SystemVerilog Design, (2) SystemVerilog
Testbenches, (3) SystemVerilog Assertions and (4) SystemVerilog C Interface and APIs.
Click here
for a detailed agenda on the SystemVerilog workshop.
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World
Wide Functional
Verification Seminar Series [more...]
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Programmable World 2003
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May 6, North America
May 15, Europe
Register
today!
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| Design
Automation Conference 2003 |
| June
2 - 5, Anaheim |
| Attend
a suite demonstration in the design area of functional verification.
Available sessions:
ModelSim 2003 - Advanced Verification and Debugging
HDL and C/C++ Design Productivity with ModelSim
Seating is limited. Sign
up today!
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FPGA Entire Desgin Flow
Training
Altera Front-to-Back Design Flow with Precision RTL
June 10, San Jose
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