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 Your Resource for Design Tools March 31, 2004 

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Spotlight
ModelSim 5.8c is now available.

This is the 3rd release in the 5.8 series and in addition to useful patches and enhancements, there are great 5.8 features available. If this is your first 5.8 release, the highlights include but are not limited to:

  • Dramatic improvement in Verilog RTL and Gate performance
  • Verilog 2001 support
  • Initial support for SystemVerilog. ModelSim is the only simulator that is currently shipping a version with SystemVerilog support.
  • Advanced Code Coverage
  • The only tri-lingual simulator on the market with support for VHDL, Verilog and SystemC that allows you to debug SystemC code in the same environment as VHDL and Verilog.
  • 100X plus improvement in waveform viewing performance. The larger the dataset the greater the performance improvement.
  • New Memory Window

Here are more features too numerous to list.
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Release Information 
ModelSim 5.8c

FormalPro™ 5.1_5a

For information on Mentor Graphics Formal Verification tool, FormalPro, please click here.

5.8 Technical Notes 

Standards Corner 

SystemVerilog 3.1a

When Accellera approved SystemVerilog 3.1 in 2003, it entered a stabilization phase where implementation of tools and use of the language by the engineering community would drive refinement and enhancements.  This process has resulted in the SystemVerilog 3.1a draft specification that the Accellera technical team has just finished writing. A final review of this draft will be initiated shortly.  

Dennis Brophy, Director of Strategic Business Development
If you would like to review and comment on Draft 5 of SystemVerilog 3.1a, download a copy of the specification.  Additions and modifications to 3.1a were thoroughly designed, reviewed and analyzed before inclusion in the draft.  SystemVerilog 3.1a improvements include alignment of SystemVerilog Assertions (SVA) with Accellera’s Property Specification Language (PSL) and use of assertions within both design code and testbench code.  The SystemVerilog Direct Programming Interface (DPI) was extended to permit time consumption by the called C/C++ function.  The verification elements of the SystemVerilog specification have been extended to include functional coverage support.  The SystemVerilog 3.1a draft provides language constructs for easy specification of functional coverage models.  These, and many other changes can be reviewed by downloading the draft.
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ModelSim 5.8 Seminars 

Ft. Lauderdale, FL 
April 20, 2004

Melbourne, FL 
April 21, 2004

San Jose, CA 
April 27, 2004

Chicago, IL 
April 28, 2004

Minneapolis, MN 
May 12, 2004

Cleveland, OH
May 19, 2004

User2User - Mentor User Conference

Santa Clara, CA 
April 19 - 21, 2004

Rapid Embedded System Design & Optimization

Worldwide 
April 29 - May 21, 2004

UK & Benelux 2004 Designer Forums

A special event focusing on the technical challenges for EDA whilst designing electronic systems. 

Manchester, England 
April 20, 2004

Veldhoven, The Netherlands 
April 22, 2004

Camberley, England 
May 5, 2004

Livingston, Scotland 
May 18, 2004

Dublin, Ireland 
May 20, 2004

Cambridge, England 
June 16, 2004