Simulation Newsletter - SystemVerilog User Group Fall Meetings

If you're a SystemVerilog enthusiast or just looking to expose yourself to SystemVerilog, then meet with your peers at an SVUG event starting next week. They've scheduled tutorials for those just getting started with SystemVerilog, presentations to improve your SystemVerilog OOP skills, user provided tips & tricks and even a "stump the experts" panel, in which you'll submit your toughest SystemVerilog questions that you've always wanted answered.

SystemVerilog User Group Meetings will be at the following locations:

Register for a meeting near you by selecting one of the event locations above.

Featured Events

Getting Started with Advanced Verification Techniques Seminar

This presentation will walk you through strategies for adopting valuable verification methodologies using standard languages that are natively supported by Questa.

Mentor Graphics' inFact testbench automation solution is the first to use intelligent algorithms to synthesize meaningful testbench sequences while allowing the user to set verification goals prior to simulation and determine verification priorities.

How intelligent testbench automation tools can help you rapidly reach higher verification coverage
How inFact's capabilities allow the creation of scalable, re-usable verification components
How intelligent testbench components fit into your overall verification architecture
How to construct an inFact intelligent testbench using step-by-step, hands-on exercises with a simple example

Learn, Share and Network with hundreds of your peers at User2User 2008, the Mentor Graphics International User Conference held at the Santa Clara Marriott.

Getting Real with OVM
Tuesday, November 4th, 2008 | 1:00 PM - 5:00 PM
Tom Fitzpatrick, Verification Technologist, Mentor Graphics

This workshop will present a full technical introduction to the Open Verification Methodology including usability and debug enhancements in Questa®. It then looks ahead to map out its future development direction. The scope and content is therefore suitable for both new users to the OVM and for those who have already had some exposure.

September 24, 2008		model.com \| latest release \| contact us \| verification horizons

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Standards Corner OVM 2.0 Available for Download The Open Verification Methodology (OVM) version 2.0 has recently been completed and made available for general industry download and use. OVM 2.0 includes a new User Guide, which provides step-by-step guidelines to help users develop reusable, interoperable verification IP, and hierarchical environments to facilitate plug-and-play verification. The release also enhances the OVM sequential stimulus mechanism in OVM with transaction-level modeling (TLM) interfaces to improve modularity and reuse of stimulus support for TLM connections throughout the hierarchy. The OVM User Guide offers comprehensive documentation on all aspects of the OVM, including an extensive review of TLM for verification, guidelines to develop reusable OVM verification components, instructions to build verification tests, and an in-depth discussion on the more advanced features of OVM. Visit OVM World to download OVM 2.0 and the accompanying User Guide. - Dennis Brophy Dennis Brophy is the Director of Strategic Business Development for the Design Verification and Technology Division at Mentor Graphics. Release & Resources ModelSim Designer 6.3f Download Latest Release Request Eval License Designer Demos Designer Datasheet ModelSim - 6.4a (new) Download Latest Release Request Eval License ModelSim Datasheet ModelSim Comparison Chart Verification Methodology AVM Cookbook v3.0-update-4 is now available. Technical Training ModelSim HDL Simulation ModelSim Advanced Topics SystemVerilog for Verification SystemVerilog Open Verification Methodology Additional Events EDA Tech Forum Oct. 1st - Boston, MA Oct. 14th - Denver, CO SystemVerilog for FPGA Designers Oct. 23rd - San Jose, CA DO-254 Pitfalls and Solutions - Webex Series Oct. 6th - Online Oct. 7th - Online Oct. 8th - Online Oct. 9th - Online Oct. 10th - Online ADMS - Mixed Signal SoC Design Workshop Oct. 16th- San Jose, CA Prototyping: Easing the Transition from ASIC to FPGA Design Oct. 16th - San Jose, CA ARM Developers' Conference Oct. 7th - Santa Clara, CA
		Informant Spotlight SystemVerilog User Group Fall Meetings Get Exposed to SystemVerilog If you're a SystemVerilog enthusiast or just looking to expose yourself to SystemVerilog, then meet with your peers at an SVUG event starting next week. They've scheduled tutorials for those just getting started with SystemVerilog, presentations to improve your SystemVerilog OOP skills, user provided tips & tricks and even a "stump the experts" panel, in which you'll submit your toughest SystemVerilog questions that you've always wanted answered. SystemVerilog User Group Meetings will be at the following locations: Ottawa, ON Brookstreet Hotel Monday, September 29th, 2008 Boston, MA Cafe Escadrille Tuesday, September 30th, 2008 Austin, TX Cool River Cafe Thursday, October 2nd, 2008 San Jose, CA Network Meeting Center at Techmart Friday, October 3rd, 2008 Munich, DE Sofitel Bayerpost Tuesday, October 28th, 2008 Register for a meeting near you by selecting one of the event locations above. Featured Web Seminars Adopting Assertion Based Verification Web Seminar Tuesday, September 30th, 2008 12:00 PM - 1:30 PM \| Central Daylight Time Increase your Simulation and Debug Performance, ModelSim Vendor Versions vs. PE and SE Web Seminar Tuesday, October 7th, 2008 12:00 PM - 1:30 PM \| Central Daylight Time Featured Events Getting Started with Advanced Verification Techniques Seminar This presentation will walk you through strategies for adopting valuable verification methodologies using standard languages that are natively supported by Questa. October 8th - Irvine, CA October 9th - San Diego, CA Featured Workshop Intelligent Testbench Automation Workshop Mentor Graphics' inFact testbench automation solution is the first to use intelligent algorithms to synthesize meaningful testbench sequences while allowing the user to set verification goals prior to simulation and determine verification priorities. You Will Learn: How intelligent testbench automation tools can help you rapidly reach higher verification coverage How inFact's capabilities allow the creation of scalable, re-usable verification components How intelligent testbench components fit into your overall verification architecture How to construct an inFact intelligent testbench using step-by-step, hands-on exercises with a simple example Locations: September 25th - Waltham, MA September 30th - San Jose, CA October 7th - Columbia, MD User2User 2008 November 4-6, 2008 Learn, Share and Network with hundreds of your peers at User2User 2008, the Mentor Graphics International User Conference held at the Santa Clara Marriott. Featured Technical Workshop at User2User Getting Real with OVM Tuesday, November 4th, 2008 \| 1:00 PM - 5:00 PM Tom Fitzpatrick, Verification Technologist, Mentor Graphics This workshop will present a full technical introduction to the Open Verification Methodology including usability and debug enhancements in Questa®. It then looks ahead to map out its future development direction. The scope and content is therefore suitable for both new users to the OVM and for those who have already had some exposure. Early Bird pricing ends October 3rd. Learn more and register. Verification Newsletter Sign up for monthly Verification News updates Start your Verification Horizons quarterly subscription