September 10, 2007
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The IEEE Design Automation Standards Committee has formed a study group to explore the creation of an IEEE encryption standard based on work done at the VSI Alliance (VSIA) to extend current IEEE encryption definitions. The study group formed as the VSIA announced it will cease operations and donate key product to the IEEE.
As leading IP suppliers seek enhanced encryption features to improve collaboration by IP providers and integrators within end user markets, ModelSim supports the new IEEE 1364™-2005 Verilog standard’s encryption definition today. The standard defines encryption in terms of protected envelopes. The protected envelopes usage model is the recommended methodology for users of Verilog’s pragma protect compiler directives.
To make it easier to use, ModelSim offers IP vendors a new utility, vencrypt, to deliver Verilog and SystemVerilog code containing undefined macros and directives.
The IP code can be used in a wide range of EDA tools and design flows. (Encryption for VHDL continues to be via the use of vcom –nodebug.)
While standards evolve to protect your source code and reduce the number of independent schemes developed by IP suppliers, we will update ModelSim. But today, IP suppliers should consult the ModelSim documentation on Protecting Your Source Code, to learn more about the new vencrypt command for Verilog and SystemVerilog to take advantage of encrypted IP sharing.
- Dennis Brophy
Dennis Brophy is the Director of Strategic Business Development for the Design Verification and Test division at Mentor Graphics.
Release & Resources
ModelSim Designer
ModelSim - 6.3bCadence and Mentor Graphics announced that they will standardize on a verification methodology based on the IEEE Std. 1800™-2005 SystemVerilog standard. The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability. It delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows. The OVM will include a robust class library and be available in source code format.
Read more!
Featured Paper: Using ModelSim for DO-254 Projects
Are you doing design work for mil-aero projects? Do any of these designs have to be DO-254 compliant? If so, we can help you get through the tool assessment process. If you are a ModelSim customer, and would like to better understand tool assessment/qualification and how to get through the process, you can request our new white paper on this topic.
Local Seminars & Workshops
- Algorithmic Generation - September 26th - Durham, NC
- ADMS: Mixed Signal SoC Design - October 16th - San Jose, CA
- EDA Tech Forum - September 12th - Santa Clara, CA
- FPGA Workshop Series - Multiple events & dates in San Jose, CA
- View the Events Calendar
Technical Papers
- Planning Formal Verification Closure
- DO-254: Understanding the Issues that Impact Business
- Effective Functional Verification Methodologies for DO-254
- Solving the Verification IP Re-Use Paradox
- View all Technical Papers
Online Events
- Maximizing ModelSim
- A Structured Approach to Effective Verification Closure
- Advanced Verification with Questa
- View Online Event Library
Training
- ModelSim HDL Simulation
Learn how ModelSim supports HDL behavioral simulations, and some basic concepts in the digital design flow. - ModelSim Advanced Topics
Capitalize on the extensive capabilities of ModelSim to effectively and efficiently analyze and debug digital HDL designs- attend training closest to you. - Contact us for questions and registration.
Verification Newsletter