August 3, 2007

  

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Standards Corner

Accellera’s Open Verification Library (OVL) 2.0 was approved as an Accellera standard recently. OVL improves electronic design quality and supports Assertion-Based Verification (ABV) with Verilog, SystemVerilog, VHDL and the Property Specification Language (PSL). OVL 2.0 is available now for download at the Accellera website. More information and examples are available at the OVL Users’ site.

OVL includes 50 assertion checkers that cover many of the common properties that engineers check during functional verification. It extends OVL by adding synthesizable checkers with new enable/fire ports for additional control of the checkers when used in hardware flows including emulation, FPGA prototyping or ASIC error detection. There are 17 new and more advanced checkers, an initial VHDL implementation, and enhanced handling of X checking. Version 2.0 is backward compatible with previous versions of Accellera OVL.

- Dennis Brophy

Dennis Brophy is the Director of Strategic Business Development for the Design Verification and Test division at Mentor Graphics.

Release & Resources

ModelSim Designer

ModelSim Verification Newsletter 		 
Informant Spotlight: Verification Survey

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Featured Workshop: Verification Management

Functional verification challenges continue as designs grow in size and complexity.  Verification environments also continue to advance as verification techniques enabled by standard hardware verification languages become main stream. Collecting and analyzing information from these broad set of tools and techniques becomes more critical to meeting product schedules and project success.  The Questa verification platform does enable the best verification techniques. This hands-on Questa Verification Management workshop will give you confidence that you can efficiently gather information, effectively analyze and easily report progress against your verification plan’s goals.

Join us in San Jose, CA on August 15th

Seating is limited, register today!

Featured Seminar: Getting Started with Advanced Verification Techniques
This seminar will include the following topics:

  • Improve the quality of your designs with assertion-based verification
  • Boost your productivity with testbench automation and constrained-random verification
  • Figure out when you are done verifying your design with coverage-driven verification
  • Learn to use verification management to develop a closed loop process that ties all activities back to your original verification plan

Find out how you can start applying these techniques now without drastic changes to your existing environment. We will also show you how to build an infrastructure for future development, that takes full advantage of these powerful concepts.

Join us in Irvine, CA on August 9th

Learn more and register .

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