June 29, 2007
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DAC 2007 featured a low power workshop on the Accellera UPF standard. The technical workshop explored low power design issues and solutions based on the Accellera UPF standard. A copy of the workshop presentations (.pdf, 3.5mb) is available at the Accellera website for those who were unable to attend DAC and would like to learn more about UPF.
A Quick Reference Guide (.pdf) has also been created and made available for those who would like a simple desktop reference.
UPF enjoys wide industry support and adoption. At DAC 2007 the UPF booth supported product demonstrations from many companies to highlight low power data portability and tool interoperability. A solutions guide (.pdf) that includes information on broad industry support can also be found at the Accellera website.
Mentor highlighted support for verification of designs that incorporate UPF power specifications to capture power management architecture. Through accurate modeling and support of the effects of switching of power domains as well as powerful capabilities of accurate modeling of retention functionality at the RT Level, we showed how Mentor verification technology was able to find and fix problems in the power management design before it was committed to implementation.
- Dennis Brophy
Dennis Brophy is the Director of Strategic Business Development for the Design
Verification and Test division at Mentor Graphics.
Release & Resources
ModelSim Designer
ModelSim Verification NewsletterModelSim is the industry leading high performance and capacity HDL simulator. Learn how to leverage the best performance and debug features of the latest release. ModelSim’s new performance capabilities target both FPGA and SoC flows in many ways. There are also new methodologies in Verification Management that allow you to tune your verification throughput. Learn about ranking coverage results to easily eliminate tests that contribute little or no new coverage. Of course we realize that everyone needs to debug and ModelSim continues to deliver debug value with new features. Post processing debug capabilities, textual dataflow, SV dynamic debugging are just a few of them. We will also discuss new language features that are now supported. Join us in this technical discussion so that you can best utilize these valuable features.
- Wednesday July 18th - 8:00 AM PST
| Next Generation in Verification Seminar Tour These seminars will focus on the methodology, tools and infrastructure you'll need to build up your planetary defenses to handle those large verification projects headed your way. By architecting Questa and the Advanced Verification Methodology (AVM) to provide revolutionary productivity and predictability benefits in an evolutionary way, Mentor Graphics is uniquely positioned to help you achieve your goals, both technically and organizationally.
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Featured Online Events
- A Structured Approach to Effective Verification Closure
- Advanced Verification with Questa
- View entire Online event library
Featured Local Seminars & Workshops
- Advanced Functional Verification Seminar - July 11th - Atlanta, GA
- Testbench Frameworks Seminar - July 25th - Durham, NC
- FPGA Equivalence Checking - Aug 13, 2007 : San Jose, CA
- Assertion Libraries Seminar - Aug 29, 2007 : Durham, NC
- FPGA Workshop Series - Multiple events & dates in San Jose, CA
Featured Technical Papers
- Using Strong Types in Your SystemVerilog Design and Verification
- Combining ModelSim and Simulink in an Integrated Environment
- Effective Implementation of Processor-driven Testbenches
- Solving the Verification IP Re-Use Paradox
Technical Training Opportunities
Check out the upcoming courses already scheduled, or contact us at education_services@mentor.com to schedule a class in your area.
- SystemVerilog for Verification
For Verilog users ready to jump into SystemVerilog! - Verilog Fundamentals for SystemVerilog
- SystemVerilog Assertions (SVA)
- ModelSim HDL Simulation
- ModelSim Advanced Topics