Informant - April 2007

April 30, 2007	model.com \| latest release \| contact us \| verification horizons

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Sections: Standards Corner \| Release Information \| Resource Center \| Training \| Events
Standards Corner The IEEE has assigned project number 1801 for the low power design and verification standard and has authorized the creation of the Low Power Study Group. The IEEE will leverage Accellera’s Unified Power Format (UPF) as the basis of their standard. UPF can still be downloaded (.pdf) for free from Accellera if you do not already have a copy. The IEEE’s project scope is to create a standard that establishes a format used to define the low power design intent for electronic systems and electronic intellectual property. The format will provide the ability to specify supply networks, switches, isolation, retention and other aspects relevant to power management of an electronic system. The standard will define the relationship between the low power design specification and the logic design specification captured by standard hardware description languages like VHDL, Verilog and SystemVerilog. If you would like to join or monitor the work of the IEEE Low Power committee, just send email to majordomo@eda.org with the word “subscribe p1801” in the body of the email message. You can also access DATE 2007 presentations from the UPF Workshop at the Accellera site for more technical details and EDA industry product implementation plans. - Dennis Brophy Dennis Brophy is the Director of Strategic Business Development for the Design Verification and Test division at Mentor Graphics. Release Information ModelSim Designer Download Latest Release Designer Datasheet ModelSim Download Latest Release ModelSim SE Datasheet ModelSim PE Datasheet ModelSim Comparison Chart Resource Center ModelSim Designer View the ModelSim Designer demos. ModelSim View the ModelSim demos. Verification Newsletter Register for monthly Verification updates and the quarterly Verification Horizons newsletter.	Come See Us at DAC!
	June 4th - 8th San Diego Convention Center Mentor Graphics - Booth #3676 Verification continues to be a major challenge with a plethora of tools, languages, and different verification platforms available to the customer. We will have multiple activities including booth demos, suite sessions, panels and more to highlight Questa, our Advanced Verification Solution and Methodology, in addition sessions on Low Power, CDC, Formal Verification and more. Register to attend a session today.
	Coming Events
	Advanced Design Techniques for FPGAs Schaumburg, IL - May 8th Detroit, MI - May 10th Minneapolis, MN - May 17th This seminar will go into the specific features that ModelSim PE and SE provide above what is available in the silicon vendor version of ModelSim commonly provided by Altera, Lattice and Xilinx. If you are seeking increased functionality or just need a lot more performance to get your designs done, then this seminar is for you. Learn more and register. Concept to FPGA to Board Seminar San Jose, CA - May 23rd This seminar will cover the all aspects of FPGA Design and PCB design to form an integrated system design. We will also explore how to bridge the FPGA design and PCB design so engineers can concurrently develop FPGA and PCB to ensure first pass success on the system.. Learn more and register. Transaction Level System Modeling Irvine, CA - May 31st Transaction Level Modeling (TLM) is one of the main components of Electronic System Level (ESL) design methodologies. Mentor Graphics has developed solutions that significantly ease the development of a TLM-based system model. These tools will enable you to create SystemC TLMs and rapidly assemble them into a system model for the purposes of architectural exploration, performance analysis, and system level-verification. Attend this workshop to learn about these system-level modeling solutions. Learn more and sign up. FPGA Workshop Series in San Jose SystemVerilog for FPGA Designers Prototyping: Easing the Transition from ASIC to FPGA Design 7 Habits of Successful FPGA Design Request your seat today. EDA Tech Forum Dallas, TX - May 1st Ottawa, ON - May 24th Networking with your EE Design peers Industry expert keynote Vendor Fair showcasing solution provider tools Hands-on workshops to test new products Cocktail reception with prize giveaway Learn more and register. Training with Education Services SystemVerilog Advanced Verification Methodology (AVM) – Get beyond the cookbook This intensive, practical course is intended for Verification Engineers ready to use the Advanced Verification Methodology (AVM) using SystemVerilog. The course is scheduled is some cities, and can be delivered in almost any region. May 10, Dallas June 13, Phoenix June 26, Longmont ModelSim HDL Simulation May 1, Dallas May 30, Longmont June 12, San Jose ModelSim Advanced Topics May 2, Dallas May 31, Longmont June 13, San Jose Not in North America? Take a look at the upcoming classes in your region. Contact us at education_services@mentor.com
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