Informant - March 2007

March 28, 2007	model.com \| latest release \| contact us \| verification horizons

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Sections: Standards Corner \| Release Information \| Resource Center \| Training \| Events
Standards Corner Accellera’s Interface Technology Committee (ITC) has ratified its second version of the Standard Co-Emulation Modeling Interface (SCE-MI) reference manual. With this ratification, a month long comment period has opened within Accellera. You can download (.pdf) a review the specification as well. SCM-MI V2 makes advances by leveraging the SystemVerilog Direct Programming Interface (DPI) that was created to allow a highly efficient connection of an HDL model with a C model. Since this is very similar to the goals of SCE-MI, the SystemVerilog DPI interface method was adopted for version 2. By using the SystemVerilog DPI scheme and adding additional capabilities to facilitate the efficient connection of the host based coed with an emulator through additional mechanisms such as pipes, the user enjoys coding simplifications over the first version. - Dennis Brophy Dennis Brophy is the Director of Strategic Business Development for the Design Verification and Test division at Mentor Graphics. Release Information ModelSim Designer Download Latest Release Designer Datasheet ModelSim Download Latest Release ModelSim SE Datasheet ModelSim PE Datasheet ModelSim Comparison Chart Resource Center ModelSim Designer View the ModelSim Designer Demos ModelSim View the ModelSim Demos Verification Newsletter Register for monthly Verification updates and the quarterly Verification Horizons newsletter Training with Education Services SystemVerilog Advanced Verification Methodology (AVM) – Get beyond the cookbook This intensive, practical course is intended for Verification Engineers ready to use the Advanced Verification Methodology (AVM) using SystemVerilog. The course is scheduled is some cities, and can be delivered in almost any region. April 17, Dallas May 23, Longmont June 13, Phoenix ModelSim HDL Simulation May 1, Dallas June 11, San Jose ModelSim Advanced Topics May 2, Dallas June 13, San Jose Not in North America? Take a look at the upcoming classes in your region. Contact us at education_services@mentor.com EDA Tech Forum Long Beach , CA - April 3rd Tempe, AZ - April 12th Networking with your EE Design peers Industry expert keynote Vendor Fair showcasing solution provider tools Hands-on workshops to test new products Cocktail reception with prize giveaway Learn more and register	See us at DATE, April 16th - 20th, Nice, France
	The ONLY European Event for Electronic System Design & Test. Once again, Mentor Graphics is sure to be the main attraction at the DATE-conference exhibition. With our wide range of best-in-class solutions, we have what you need for today's most challenging design problems. Come and meet us on our Booth M3 level 1. For more information visit our website. Featured at DATE - Solution Workshop: Using SystemC and SystemVerilog together in an Advanced Verification Methodology Thursday 19th April, 11:00 - 12:30 Lunch 12:30 - 13:00 This Workshop will discuss functional verification methodology using the Advanced Verification Methodology (AVM) as an example of how SystemC and SystemVerilog can be combined within a single coherent environment to support assertions, functional coverage, stimulus generation, and transaction-level modeling. More information and register for this workshop. Featured at DATE - Accellera Low-Power Lunch Workshop April 17 - Nice, France Novotel, Matisse/Chagall Conference Room How will you define, verify and implement your next low power design? Join Mentor Graphics, Synopsys and Magma for an educational lunch seminar on Accellera's Unified Low Power Format (UPF) standard. See how UPF extends logic design specifications with low power information such as isolation and retention strategies, power domain definition, supply distribution and switching for verification and implementation. More information and registration for this workshop.
	Coming Events
	SystemVerilog Assertions Seminar - How To Leverage It Today San Diego, CA - March 30th El Segundo, CA - April 13th This seminar is an introduction to what Assertions are, with examples of how to use them to improve your Verification environment today. Learn more and register. Advanced Design Techniques for FPGAs Seminar Portland, OR - April 10th Seattle (Redmond), WA - April 11th Coquitlam, BC - April 12th The seminar will discuss the latest ModelSim design features to take you to the next level, including exploiting advanced verification techniques to more efficiently manage functionally verifying millions of gates. Learn more and register. Integrated Firmware/Hardware Debug for Processor Driven Testbenches Seminar San Jose, CA - April 12th Mentor Graphics offers a ModelSim/Questa fully integrated source-level debugger that attaches to signoff and cycle-accurate ARM processor models, thus delivering a unified firmware/hardware debug environment. In this seminar we will present and demonstrate this capability. Learn more and register. SystemVerilog Constrained-Random Verification Seminar San Jose, CA - April 18th In the current verification environment engineers write directed tests to verify the functionality of their design. Once functionality has been verified they add more tests to the suite. Quite often this process is time consuming and many corner cases are missed. Learn more and register. Eliminating Clock-Domain Crossing Bugs with 0-In CDC Workshop Austin, TX - March 29th Minneapolis, MN - April 4th This hands-on workshop teaches attendees about the types of problems associated with clock domain crossings, the things you can do to avoid these issues, and how to apply an automated verification solution to ensure your design is free of CDC issues. More information and reserve your spot. Improving Verification Results with 0-In Formal Verification Workshop Austin, TX - March 29th Minneapolis, MN - April 4th With a focus on methodology for success, along with hands-on tool usage, this ½ day workshop is a must for anyone entertaining the idea of evaluating formal verification tools and/or using formal verification on their next project. More information and reserve your spot. IP-XACT™ Specification Enables Rapid, Reliable FPGA and Processor-based Design Embedded Systems Conference - April 3rd Join ARM and Mentor Graphics as they present a range of verification options that will allow you to validate the correctness and functionality of generated design for different targets. Learn more and register. FPGA Workshop Series in San Jose SystemVerilog for FPGA Designers Prototyping: Easing the Transition from ASIC to FPGA Design 7 Habits of Successful FPGA Design Avoiding Costly FPGA Re-spins Request your seat today. ModelSim User Conference Berkshire, UK - April 25th Saros is hosting their annual ModelSim User Conference to provide technical update to existing users on the ModelSim tool. The day will also consist of sessions introducing the latest methodologies for the design and verification of complex ASIC and FPGA devices. Learn more.
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