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March 1, 2007 | |
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Hello {vchFirstName}, Thank you for subscribing to the Informant, the newsletter that focuses on bringing you technical information on Simulation products from Mentor Graphics®. You can update your preferences at anytime at the Informant site by specifying your email address and your password. |
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Sections: Standards Corner | Release Information | Resource Center | Training | Events |
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Standards CornerAccellera has approved the Unified Power Format (UPF) 1.0 document as an Accellera standard. The UPF standard is a convergence of proven technology donations from seven companies, including Mentor Graphics. Strong collaborative participation by Accellera members and other dedicated companies resulted in an open standard that was developed in only 5 months.UPF defines how to create a supply network to supply power to each design element, how the individual supply nets behave with respect to one another, and how the logic functionality is extended to support dynamic power switching to these logic design elements. By controlling the operating voltages of each supply net and whether the supply nets and their connected design elements are turned on or off, the supply network will provide power at the level the functional areas of the chip need to complete the computational task in a timely manner. The “Power of One” standard to bring the industry together will drive greater design and verification productivity. Design and verification engineers can look forward to portable low-power design and verification data, multi-vendor tool interoperability and more advanced low-power flows. To help you learn about the value of “Power of One” standard and be ready to use tools that support UPF, UPF 1.0 has been made available free of charge for download (.pdf) from Accellera. - Dennis Brophy Dennis Brophy is the Director of Strategic Business Development for the Design
Verification and Test division at Mentor Graphics.
SystemVerilog User GroupA new community created by users for users that is entirely dedicated to SystemVerilog. Get exposed to SystemVerilog at www.svug.org Release InformationModelSim DesignerModelSimResource CenterModelSim DesignerModelSimVerification NewsletterTraining with Education ServicesSystemVerilog Advanced Verification Methodology (AVM) This intensive, practical course is intended for Verification Engineers ready to use the Advanced Verification Methodology (AVM) using SystemVerilog. The course is scheduled is some cities, and can be delivered in almost any region. ModelSim HDL Simulation ModelSim Advanced Topics Not in North America? Contact us at education_services@mentor.com |
Improving Your Verification Throughput |
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Everyone wants improved time to silicon verification. There are many things that contribute to meeting verification plan’s goals and Mentor Graphics has been steadily improving our customer’s productivity in many ways. The traditional measurement of verification has been raw simulation run time. Mentor’s simulation performance is gained by using the vopt performance flow. This global performance optimization step includes all our natively supported languages, Verilog, SystemVerilog, VHDL and SystemC. ModelSim is a Single Kernel Simulation engine with one event wheel. This potent combination goes beyond the elimination of non-native implementations that require a PLI, DPI for a Foreign Language Interface. Vopt provides a global opportunity to optimize everything in your verification environment. Beyond these broad performance opportunities, we generate native code for your particular hardware platform. Even with the traditional definition of verification performance as raw simulation run time, there are many ways to achieve performance. Continue to monitor this publication for future performance hints. For many there is no substitute for raw simulation performance. However there are other considerations that many users should consider: functional coverage, assertion density and coverage. Just like traditional code coverage using these methodologies will create large amounts of data. To verify these you need to be able to directly linking the coverage results to the original verification test plan. How many tests in your regression suite contribute to your coverage? For more information about improving the simulation run time, see chapter 3 “Optimizing Designs with vopt” (.pdf) on page 111 in the Users Guide. |
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ADMS: Mixed-Signal SoC Design and Verification WorkshopSan Jose, CA - March 8thIn this workshop we will explore the current trends of IC design and highlight the challenges these trends create. This workshop will expose you to comprehensive solutions necessary to improve your design and verification productivity. Limited seating, learn more and signup. Eliminating Clock-Domain Crossing Bugs with 0-In CDC WorkshopSan Jose, CA - March 9th This hands-on workshop teaches attendees about the types of problems associated with clock domain crossings, the things you can do to avoid these issues, and how to apply an automated verification solution to ensure your design is free of CDC issues. If your design's high quality goals, short schedule, and/or tight budget can't afford the hit of a CDC bug and youre ready for a solution to help, this ½ day workshop is for you. More information and reserve your spot Improving Verification Results with 0-In Formal Verification WorkshopSan Jose, CA - March 9th With a focus on methodology for success, along with hands-on tool usage, this ½ day workshop is a must for anyone entertaining the idea of evaluating formal verification tools and/or using formal verification on their next project. More information and reserve your spot. Advanced Verification with Questa SeminarLongmont, CO - March 28th This presentation introduces the audience to the verification concepts required to support an Advanced Functional Verification Methodology. Topics covered include:
More information and to register. Transaction-level System Modeling (ESL) WorkshopSan Jose, CA - March 28th
Limited seating - learn more and sign up. ModelSim User ConferenceBerkshire, UK - April 25thSaros is hosting their annual ModelSim User Conference to provide technical update to existing users on the ModelSim tool. The day will also consist of sessions introducing the latest methodologies for the design and verification of complex ASIC and FPGA devices. Mentor Graphics User2UserSan Jose, CA - March 14th, 15thLearn, Share and Network with hundreds of your peers at User2User 2007. Learn
Share
More information and register. |
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