Informant - January 2007

February 1 , 2007	model.com \| latest release \| contact us \| verification horizons

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Sections: Standards Corner \| Release Information \| Resource Center \| Training \| Events
Standards Corner UPF Approved by Accellera TSC This is good news for the industry as power constraints drive the design of most ASICs today. A standard for specifying low power design intent for use in functional verification and implementation -- synthesis and place and route -- fills a hole as the specification of power distribution, power control, isolation, retention and level shifting are not part of the scope of HDLs like SystemVerilog and VHDL. UPF has broad industry support with technical donations from 8 different companies including Mentor Graphics, Synopsys, Magma, Atrenta and multiple users. Mentor Graphics will be working with our UPF partners to bring educational seminars starting with an embedded tutorial at DVCon in February. Check the Mentor Graphics functional verification website for up-to-date information and announcements on future UPF events. - Stephen Bailey Stephen Bailey is the Vice Chair of the Accellera VHDL TC and the Product Marketing Manager for ModelSim at Mentor Graphics. Release Information ModelSim Designer Download Latest Release Designer Datasheet ModelSim Download Latest Release ModelSim SE Datasheet ModelSim PE Datasheet ModelSim Comparison Chart Resource Center ModelSim Designer View the ModelSim Designer demos. ModelSim View the ModelSim demos. Verification Newsletter Register for monthly Verification updates and the quarterly Verification Horizons newsletter. Training with Education Services SystemVerilog Advanced Verification Methodology (AVM) – Get beyond the cookbook This intensive, practical course is intended for Verification Engineers ready to use the Advanced Verification Methodology (AVM) using SystemVerilog. The course is scheduled is some cities, and can be delivered in almost any region. February 22, Baltimore ModelSim HDL Simulation February 13, Baltimore March 6, San Jose ModelSim Advanced Topics February 14, Baltimore March 7, San Jose Not in North America? Take a look at the upcoming classes in your region. Contact us at education_services@mentor.com	Mentor Graphics International User Conference
	March 14 - 15, San Jose, CA Learn, Share and Network with hundreds of your peers at User2User 2007, the Mentor Graphics International User Conference. Take advantage of Early Bird Pricing by registering today at www.mentor.com/user2user – you will save up to $200, plus be entered to win a limited edition iPod! Learn 20 no charge half day/full day hands-on workshops (up to $650 value) 120 technical sessions – 70% by customers – showcasing real world examples across 14 tracks Business/Management track for senior managers Mentor Solutions Center to see the newest product features Share Keynote sessions from Dr. Walden C. Rhines, Mentor CEO, and Craig Newmark, founder of craigslist.org Exclusive product updates from Mentor technical executives Usability Lab to provide Mentor representatives direct feedback Network Interact with 600+ engineers - understand how they have addressed your same challenges Access to Mentor technical experts More information and register.
	Coming Events
	DVCon - 2007 San Jose , CA - February 21-23 Booth #804 Join us at booth #804 to see Questa™, our advanced verification environment, as well as our 0-In® functional coverage tools. Booth demos will also include our portfolio of electronic system level (ESL) design technologies that complement the AVM to enable hardware design and verification at a higher lever of abstraction. Wednesday's Featured Tutorial - Practical Applications of AVM presented by Verification Technologist - Tom Fitzpatrick Thursday Lunch Panel - The Lowdown on Low-Power Design and Verification moderated by EE Times, EDA Editor, Richard Goering. New papers, more panels, tutorials and more. View full listing of Verification and ESL activities ModelSim 6.2 Seminar Have you seen ModelSim lately? Wednesday, February 7th - San Jose, CA ModelSim continues to evolve as the new Standard Design and Verification languages are supported. Native support of Standard languages like SystemVerilog and SystemC add significant new functionality to the Simulation kernel and User interface. ModelSim 6.2 delivers across the board with SystemVerilog for design support for more concise design descriptions to DPI capabilities and GUI enhancements that improve the analysis and debug of designs. This presentation will introduce the new features that are available in ModelSim More information & register for this event Eliminating Clock-Domain Crossing Bugs with 0-In CDC Workshop Rochester, NY - February 8th San Jose, CA - March 9th If you are serious about improving your verification methodology with Clock-Domain Crossing and/or Formal Verification techniques, you're invited to attend this limited seating, no charge hands-on workshop event. More information and reserve your spot Transaction-level System Modeling (ESL) Workshop Boston, MA - February 28th Learn how to create a Transaction-level Model (TLM) for a design component Learn how to assemble a system model from TLMs and bus models Learn how to debug and analyze the system model Limited seating - learn more and sign up Two New Workshop Series in San Jose Prototyping: Easing the Transisition from Asic to FPGA Design This workshiop includes: ASIC prototyping with FPGAs Design considerations that must be made in both the ASIC and the FPGA design to facilitate both devices Design debugging and analysis Performance enhancement techniques to provide the most realistic verification platform. 7 Habits of Successful FPGA Design Agenda: Use standard languages and constraints for design portability Design to enable FPGA device selection freedom Code for FPGA vendor independence Apply comprehensive design constraints Exercise superior optimization Utilize advanced analysis for to uncover design and timing flaws Minimize the impact of design turns San Jose – Monthly Learn more and submit your interest.
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