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October 31, 2006 | |
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Hello {vchFirstName}, Thank you for subscribing to the Informant, the monthly newsletter that focuses on bringing you technical information on Simulation products from Mentor Graphics®. You can update your preferences at anytime at the Informant site by specifying your email address and your password. |
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Sections: Coming Events | Standards Corner | Release Information | Technical Resource Center |
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Standards CornerVSIA Launches Verification IP Quality PillarWith the ever increasing demand for complex SoCs showing no slowdown as they make their way to products like iPods, wireless internet devices, automotive entertainment, cell phones and more, it is clear that companies must realize cost and time efficiencies by using third-party IP and related integrated services. According to a recent FSA study, the cost to integrate IP is three times the cost of the actual IP, which indicates that verification is still a key challenge. The complexity of Verification IP is many times greater than the actual design IP and therefore, several leading companies have banded together within VSIA to focus on Verification IP (VIP) quality measures. Mentor Graphics' Kenneth Larsen holds the VSIA Verification IP Workgroup
chairman position to establish the much needed quality metric worksheet for
VIP. This effort he leads will help you minimize risk and realize greater
productivity as you strive to develop next-generation technologies. If you
would like more information on the important VIP quality measures initiative
and to join with others to solve this problem, please visit
www.vsia.org.
Dennis Brophy is the Director of Strategic Business Development for the Design
Verification and Test division at Mentor Graphics
Release InformationModelSim DesignerModelSimTechnical Resource CenterModelSim DesignerModelSimVerification NewsletterTechnical Training with Education ServicesNot in North America? ModelSim HDL Simulation ModelSim Advanced Topics AVM customer training is now available – Get beyond the cookbook This intensive, practical course is intended for Verification Engineers ready to use the Advanced Verification Methodology (AVM) using SystemVerilog. The course is scheduled is some cities, and can be delivered in almost any region.Register online or call your local Education Services Representative. Contact us at education_services@mentor.com |
New Embedded Code Debugger |
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An optional debugger for processor driven tests is now available for ModelSim version 6.1 or later. The debugger consists of an additional set of windows that operate within the ModelSim GUI. The new source, assembly, register and variable windows provide a view into C or assembly code as it executes on a full functional processor model during simulation. The user can set breakpoints, step through C or assembly, examine the contents of software variables, and view the status of processor registers. The ability to view and interact with the code as it executes is a far more effective debug environment than viewing the waveform window and looking at static listings of the source or compiler output files like the symbol table and assembly listing. The new software debug windows maintain the same look and feel as the current ModelSim windows, so learning the embedded code debugger is quick and easy. The ModelSim embedded code debugger is available now and has been interfaced to the ARM Design Signoff Model (DSM) as well as Mentor’s Processor Support Packages (PSPs) for ARM cores. The embedded code debugger connects to the existing DSM in your design so there are no changes required whatsoever to your design or simulation models. Replacing the DSM with a Mentor PSP dramatically accelerates the execution of embedded code. The PSPs run at 200,000 instructions per second. Overall simulation speed improves by 5x to 10x depending on the ration of software execution to hardware evaluation in your simulation. The debug environment is identical with whether the DSM is used for signoff accuracy or cycle accurate PSP is used for faster simulation. For more information send your inquiries to seamless_info@mentor.com. |
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ModelSim 6.2 SeminarAttend the ModelSim 6.2 Seminar ModelSim continues to evolve as the new Standard Design and Verification languages are supported. Native support of Standard languages like SystemVerilog and SystemC add significant new functionality to the Simulation kernel and User interface. ModelSim 6.2 delivers across the board with SystemVerilog for design support for more concise design descriptions to DPI capabilities and GUI enhancements that improve the analysis and debug of designs. This presentation will introduce the new features that are available in ModelSim More Information & Register for this event FPGA Design and Signal Integrity Analysis SeminarsSchaumburg, IL -Nov. 14th Altera Corporation, Mentor Graphics and AVID Technologies together invite you to a cooperative seminar focused on FPGA Design and Signal Integrity Analysis of your designs using Altera programmable solutions. This is a focused seminar that provides attendees with information and education. Each of the sessions outlined below is designed to help designers be more productive with the design environment to obtain accelerated time to market (which translates to accelerated time to profits) for their products. More Information and Register for this event Accelerating RTL Reuse SeminarDo you use code from a previous design or an outsourced group? You are invited to participate in this seminar to learn new techniques that can help you quickly understand and reduce the effort required to reuse code. Let us show you how to do this in 3 easy steps:
Location & Dates: More information and registration Achieving Timing Closure in FPGAs with Precision Synthesis: Hands-on WorkshopStart Designs Right, Improve Designs Faster, Meet Project Requirements
Locations and Dates: More Information and registration. Verification of MIPS-based design SeminarSan Jose, CA - Nov. 15th from 11:00 to 1:30 Mentor Graphics and MIPS jointly deliver a solution to take advantage of the high-performance, MIPS 24K processor while minimizing design time and reducing product costs.
ModelSim User's DayParis, France - Wednesday, Nov. 15th (9:15 am - 4:30 pm) Salons Etoile Saint Honoré Electronica 2006Munich, Germany - Nov. 14th - 17th See Mentor at Electronica in Munich! Visit us in Hall A1 booth 331 0-In SeminarMunich, Germany - Nov. 30th Design complexity is pushing traditional functional verification techniques to the limit, and technologies such as Formal Verification and Clock Domain Crossing (CDC) verification are rising to meet the challenge. Solutions ExpoHerzliya, Israel - Nov. 21st During one day, you will have the opportunity to meet with senior Mentor Graphics management and experts from our technical teams. The conference is open to both customers and the design community (Engineers and Managers), allowing you to share design and system integration experiences with engineers from a wide variety of companies. |
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