|
September 28, 2006 | |
 |
 |
|
Hello {vchFirstName}, Thank you for subscribing to the Informant, the monthly newsletter that focuses on bringing you technical information on Simulation products from Mentor Graphics®. In conjunction with our new website design we've updated the look of the Informant as well. You can update your preferences at anytime at the Informant site by specifying your email address and your password. |
|
|
Sections: Coming Events | Standards Corner | Release Information | Technical Resource Center |
|
Standards CornerMentor Donates Technology to New Accellera Unified Power Format CommitteeAccellera, at the request of user companies such as TI and Nokia, has approved a new Technical Subcommittee (TSC) for the purpose of defining a Unified Power Format (UPF) for use in low power designs. The scope of the UPF-TSC includes specification of low power architecture information such as voltage and power domains and retention behavior, design and synthesis constraints, activity information for use in calculating power consumption, modeling styles and library data for accurate characterization of power information. Three companies, Mentor Graphics, Magma and Synopsys, have already donated technology to the UPF-TSC. Other companies have indicated their intention to donate technology as well. The technology that has been donated has been proven in production designs. The UPF-TSC anticipates the primary effort will be to unify the various approaches into a standard format that covers all low power design requirements. For more information on the UPF-TSC, check out their
public web page. To participate in the
UPF-TSC, there are links at the bottom of the page to become a member of the TSC for Accellera members
and non-members.
Steve Bailey is the Vice Chair of the Accellera VHDL TC and the Product Marketing
Manager for ModelSim at Mentor Graphics.
Release InformationModelSim DesignerModelSimTechnical Resource CenterModelSim DesignerModelSimVerification Newsletter |
Online Seminar: Harnessing ModelSim Designer to Improve Your FPGA Design Productivity |
|
This Webcast will take you through the complete process of creation, management, simulation, and implementation controlled from a single user interface, facilitating your design and verification flow and providing significant productivity gains. We will also show you how to coordinate your synthesis and place-and-route processes by allowing ModelSim Designer to automatically manage your project files, easing the downstream transition to the synthesis and place-and-route tools of your choice. Finally, we will explain how to take advantage of the extensibility of ModelSim Designer using available options like code coverage analysis, the SWIFT interface, and a profiler that helps you identify performance bottlenecks in your design. Tuesday, October 10th, 2006 |
|
User2User 2007March 14-15th, 2007, in San Jose, CA. We invite you to share your technical expertise with other Mentor Graphics users at User2User 2007, the Mentor Graphics International User Conference. The abstract submission deadline is October 31st, 2006. Each person submitting an abstract(s) by 5:00 PM PDT on October 31st, 2006 will receive a special edition t-shirt. All qualifying abstracts will be entered in a drawing to win one of three great prizes from our friends at HP including the HP 428 Compact Photo Studio, R817 HP Digital Camera, and HP iPaq rx 1955 Pocket PC. Additional Information and complete abstract submission details Advanced Verification Methodology (AVM) - Get Cookin': Recipes for Advanced VerificationThis seminar will discuss Mentor's Advanced Verification Methodology (AVM), which uses a "cookbook" approach to show you how to build reusable transaction-level testbenches in SystemVerilog and/or SystemC, that let you apply such leading-edge techniques as constrained-random simulation, functional coverage and assertions in a practical and straightforward manner. If you're wondering why it is that you've been hearing about these techniques for years, but no one's been able to show you how to apply them to your particular problem, it's because no one has been able to deliver a powerful yet easy-to-adopt methodology to handle the difficult issues of testbench architecture, modularity, and communication. Until the AVM, that is. Come join us, along with our Questa Vanguard partner Denali, to see how to verify your design at multiple levels of abstraction while effectively measuring your progress and finding more bugs than you ever thought possible. San Jose - October 25th, 2006 More information and registration Accurately Predicting and Simulating FPGA Power Levels to Reduce Power Consumption in System DesignsBy attending this seminar, hosted by Mentor Graphics and Quicklogic, you will automatically be entered to win an air/cruise package for two to ALASKA! Today's converging technologies are forcing designers to find new ways of embedding an increasing number of new features into their applications while maintaining aggressive power budgets. This seminar will focus on available techniques to enable design engineers to predict and understand all aspects of power consumption before beginning their FPGA design. Demonstrations will compare various FPGAs available in the market today, examining differences in static and dynamic power, as well as a tutorial session on how to use special low power modes and optimize clock network usage to minimize power consumption in a design. San Jose – October 11th More information and registration European Solutions Expos 2006Join us for an in-depth program that will give you the latest news about EDA tools and technologies and offer you a glimpse of what's coming. As usual you can meet and discuss with Mentor Graphics personnel, partners and colleagues.
More information and registration Hardware/Software Integration Workshop
San Jose, Oct. 12th from 9:30 to 3:30 Transaction-level System Modeling (ESL) Workshop
San Jose, Oct. 17th from 9:30 to 3:30 ModelSim TrainingNot in North America? ModelSim HDL Simulation ModelSim Advanced Topics Verilog Fundamentals for SystemVerilog This one-day class is a prerequisite for engineers who wish to take the SystemVerilog Verification class, but do NOT have a Verilog background. It will provide a basic understanding of Verilog so the student can utilize SystemVerilog for design verification SystemVerilog for Verification Customer Training Offers other Language Training Course Options |
|
 |
If you do not wish to receive future ModelSim mailings, please reply to this email message with "Optout EMAIL" in the subject. Mentor Graphics 8005 SW Boeckman Road Wilsonville, OR, 97070, USA 800-547-3000 or 503-685-8000. Please note that our privacy policy is also available. |
