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August 30, 2006 | |
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Hello {vchFirstName}, Thank you for subscribing to the Informant, the monthly newsletter that focuses on bringing you technical information on Simulation products from Mentor Graphics®. In conjunction with our new website design we've updated the look of the Informant as well. You can update your preferences at anytime at the Informant site by specifying your email address and your password. |
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Sections: Coming Events | Standards Corner | Release Information | Technical Resource Center |
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Standards CornerWhat XACTly is SPIRIT?Before you may have had an opportunity to appreciate what the SPIRIT Consortium was developing to foster IP reuse, they changed the name for the specification. As part of the hand-off of the specification from the SPIRIT Consortium to the IEEE for industry-wide standardization, SPIRIT named the standard IP-XACT. The Corporate Advisory Group (CAG) has agreed to co-sponsor the IP-XACT standardization project within the IEEE. The IEEE P1685 Working Group has begun the process of standardizing version 1.2 of IP-XACT. This version provides a metadata schema for describing IP. Tools, such as Mentor's Platform Express, that support IP-XACT, use the metadata to automate the interpretation, configuration, manipulation and integration of reusable IP blocks into electronic systems. The ability to efficiently reuse and parameterize IP blocks continues to grow as the size of designs require ever greater amounts of block reuse. The SPIRIT Consortium continues to actively look for ways to improve IP reuse. IP-XACT 1.2
defines the base capabilities required for IP defined and used at the RTL abstraction level.
Work is in progress to extend the IP-XACT specification up to the system and transaction level
for describing reusable verification as well as design IP. Mentor Graphics' SPIRIT leadership
continues as we lead the way in defining version 1.4 of IP-XACT through our SPIRIT Steering
Committee membership, and through our expanding and comprehensive support for the IP-XACT
specification.
Steve Bailey is the Vice Chair of the Accellera VHDL TC and the Product Marketing
Manager for ModelSim at Mentor Graphics.
Release InformationModelSim DesignerModelSimTechnical Resource CenterModelSim DesignerModelSimVerification NewsletterModelSim TrainingNot in North America? ModelSim HDL Simulation ModelSim Advanced Topics Comprehensive VHDL Training SystemVerilog ModelSim Users GroupMid-Atlantic Users - Attend MARLUG 2006Thursday, October 12th at Johns Hopkins Applied Physics Lab near Baltimore Make plans now to attend MARLUG, the largest and longest running Mentor Graphics Local Users Group Conference. Come join your fellow users for a day of learning, sharing and networking. Pre-conference workshops are available at no charge on Wednesday, October 11th. |
ModelSim Designer 6.1f now available |
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ModelSim Designer delivers a complete FPGA design and verification environment. Our focus is on improving your productivity which means the complete process of creation, management, simulation, and implementation is controlled from a single user interface, facilitating the design and verification flow and providing significant productivity gains. Vendor tool plugin's have been updated for version 6.1f to include support for:
The 6.1f release is now available for download. |
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ModelSim 6.2 SeminarModelSim 6.2 delivers broad SystemVerilog for design to enable more flexible design descriptions and support of the high performance DPI capabilities. The single kernel simulation engine also has a highly capable native debug environment that includes enhancements like Source Annotation and Finite State Machine extraction that improve the analysis and debug of designs. Other improvements are a new Unified Coverage Database that improves coverage capacity and improved data management capabilities. ModelSim 6.2 also sets the performance standard with significant Verilog Gate/RTL and VHDL performance. This seminar will introduce the many new features that are available in ModelSim. Date/Time: Location: Altera and ModelSim Advanced Simulation Techniques for FPGAs SeminarWith every new design, your challenge gets bigger. You're faced with creating a better solution in half the time. Advanced design techniques & high performance devices can take you to the next level in FPGA design. Whether you're tackling thousands or millions of gates, you'll approach design from a whole new perspective. Learn how to apply advanced design techniques for creating, debugging & simulating your next design. Date and Time: Location: The Hitchhiker's Guide to Verification SeminarMontreal, Quebec Canada Having a very bad day? Your last chip required a respin, you just realized that there's a whole class of bugs that your testbench just isn't set up to catch, and to top things off, you don't have enough verification engineers to write all the tests you're going to need. DON'T PANIC! Your only chance for survival: hitch a ride with a friendly team of verification experts. With The Hitchhiker's Guide to Verification seminar, you'll set out on a journey in which you'll find the secret to Life, the Universe and Everything (or at least the secret to Testbench Automation, Reuse, and Functional Coverage). Set up mostly in two parallel tracks, the day will begin with an introduction to Mentor Graphics' Advanced Verification Methodology (AVM), which greatly facilitates the development of transaction-level testbenches that can be used to verify designs at multiple levels of abstraction. More information and Register! Introducing the Advanced Verification Methodology (AVM) - Now We're Cookin': Recipes for Advanced VerificationToronto, Canada This seminar will introduce Mentor's Advanced Verification Methodology (AVM), which uses a "cookbook" approach to show you how to build reusable transaction-level testbenches in SystemVerilog and/or SystemC, that lets you apply such leading-edge techniques as constrained-random simulation, functional coverage and assertions in a practical and straightforward manner. Come and let us show you how to verify your design at multiple levels of abstraction while effectively measuring your progress and finding more bugs than you ever thought possible. More information and Register! Eliminate Clock Domain Crossing Errors in RTLFaulty management of clock-domain crossing (CDC) signals is a major cause of functional errors in silicon. Come join us over lunch as we examine how to use the 0-In CDC product to identify potential CDC problems early in the design cycle. We explore a mix of advanced technologies, which include the innovative CDC-FX metastability analysis system. Date and Time: Location: HW/SW Integration of Designs using ARM1176 ProcessorsNew Online Seminar
Presented jointly with ARM, this seminar provides an overview of the ARM1176 processor and discusses the benefits of using a virtual prototype to uncover potential errors in code prior to tape-out. Avoiding Costly FPGA Re-spins: Hands-on WorkshopModern FPGAs present huge opportunities and are opening new markets for FPGAs, but their high performance and high densities are throwing the traditional 'design-burn-and-test' process out the window. Re-spinning the design in response to a specification violation found in the lab is no longer quick and easy, but rather painful and very costly. This workshop will demonstrate effectively how to meet complex design requirements by analyzing performance and verifying functionality early and frequently throughout the design process, where the overall pain and cost for fixing errors is much less.
Achieving Timing Closure in FPGAs with Precision Synthesis: Hands-on WorkshopStart Designs Right, Improve Designs Faster, Meet Project Requirements
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