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DAC 2006

Mentor Graphics at DAC
July 24th – 28th
San Francisco, Booth # 928

Verification continues to be a major challenge with a plethora of tools, languages, and different verification platforms available to the customer. We will have multiple activities including booth demos, suite sessions, panels and more to highlight our Advanced Verification Solution and Methodology.

More information and register

SystemVerilog: Language Tutorial and Industrial Verification Experience

Friday, July 28
Moscone Convention Center, Room 307
9:00 AM - 5:00 PM

This tutorial will provide a detailed overview of the IEEE 1800 SystemVerilog Hardware Design and Verification Language (HDVL), including practical examples of industrial experience using the language to develop complex designs. The tutorial will include a thorough description of the SystemVerilog definition, intent and potential while covering the design modeling, testbench automation, verification, assertions aspects of the language, and the programming interfaces. The practical sessions will include discussions of what has worked well, the impact on design and verification productivity and transition experiences from Verilog to SystemVerilog, as well as suggestions of possible future directions for the language.

More Information and Register

Efficient Multi-vendor Design and Verification flows - Proof that they exist!

Technical Luncheon at DAC 2006!

ARM and Mentor Graphics cordially invite you and your colleagues to attend a free technical seminar at DAC. ARM and Mentor will demonstrate an advanced system-optimization and verification solution that addresses an automated flow from SystemC platform development through fabric generation to full system assembly including complex, configurable IP to software creation and full system verification.

Thursday, July 27th,
Moscone Center,
11:30am-1:30pm.

Lunch will be provided. Space is limited. First 100 attendees will receive free gift and be included in drawing for mini-iPod to be given away at the conclusion of the seminar.

Registration information

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Advanced Design Techniques for FPGAs On Demand Webcast

With every new design, your challenge gets bigger. You're faced with creating a better solution in half the time. Advanced design techniques & high performance devices can take you to the next level in FPGA design. Whether you're tackling thousands or millions of gates, you'll approach design from a whole new perspective. Learn how to apply advanced design techniques for creating, debugging & simulating your next design.

The webcast discusses the latest ModelSim design features and Altera devices to take you to the next level, including exploiting advanced verification techniques to more efficiently manage functionally verifying millions of gates.

More Information

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Avoiding Costly FPGA Re-spins: Hands-on Workshop

San Jose, CA - Monthly

Modern FPGAs present huge opportunities and are opening new markets for FPGAs, but their high performance and high densities are throwing the traditional 'design-burn-and-test' process out the window. Re-spinning the design in response to a specification violation found in the lab is no longer quick and easy, but rather painful and very costly. This workshop will demonstrate effectively how to meet complex design requirements by analyzing performance and verifying functionality early and frequently throughout the design process, where the overall pain and cost for fixing errors is much less.

Submit your interest

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ModelSim 6.2 Seminar

Wednesday, August 16
Mentor Graphics
1001 Ridder Park Drive, Room B108
San Jose, CA 95131
11:30 AM - 1:30 PM

ModelSim is the most comprehensive environment for Design and Verification. Native support of standard languages like SystemVerilog and SystemC add functionality to help solve the most complex design and verification problems. ModelSim 6.2 delivers broad SystemVerilog for design to enable more flexible design descriptions and support of the high performance DPI capabilities. The single kernel simulation engine also has a highly capable native debug environment that includes enhancements like Source Annotation and Finite State Machine extraction that improve the analysis and debug of designs. Other improvements are a new Unified Coverage Database that improves coverage capacity and improved data management capabilities. ModelSim 6.2 also sets the performance standard with significant Verilog Gate/RTL and VHDL performance.

This presentation will introduce the many new features that are available to ModelSim users.

Registration information

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ModelSim Training

Training Opportunities

Looking for training outside of North America? Search the world

ModelSim HDL Simulation

Aug 15, Baltimore

Advanced ModelSim

Aug 16 Baltimore

VHDL Comprehensive

Aug 14, San Jose