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June 29, 2006 | |
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Hello [vchFirstName], Thank you for subscribing to the Informant, the monthly newsletter that focuses on bringing you technical information on Simulation products from Mentor Graphics®. In conjunction with our new website design we've updated the look of the Informant as well. You can update your preferences at anytime at the Informant site by specifying your email address and your password. |
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Sections: Coming Events | Standards Corner | Release Information | Technical Resource Center |
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model.com updatedIn an effort to continue to fulfill your design needs as well as make your user experience as easy as possible, we have updated our web site with a new look, new features and new information! We ask that you take a few minutes to visit the new site and fill out a brief survey so that we can continue to serve your on-line resource needs. By filling out the survey you will be entered to win a special gift from ModelSim. In addition, the first 100 respondents will receive a $5 Amazon gift certificate that will be sent to you via email. Thank you in advance for your feedback and we hope you find the new site useful. Standards CornerVHDL & SystemC Specifications Available at No CostAccellera has collaborated with the IEEE to enhance and extend VHDL (IEEE Std. 1076™). As Accellera completes it work in preparation to handoff to the IEEE, the draft specification for the proposed 1076-2006 version is being made available for public comment. You can download the full package from the Accellera website. For a list of changes from IEEE Std. 1076-2002, please refer to Annex D of the draft language reference manual (LRM). Comments on the draft can be addressed to the committee at vhdl-lrm@lists.accellera.org. The Open SystemC Initiative (OSCI) has worked with the IEEE to make the new IEEE 1666™-2005 standard
available without cost to anyone. A special website has been setup at the IEEE to
download the
IEEE 1666™-2005 Standard SystemC Language Reference Manual. Any company, university, research institution
and individual are able to freely access the standard and develop applications for SystemC-based tools and
technologies.
Dennis Brophy is the Director of Strategic Business Development for the Design
Verification and Test division at Mentor Graphics
Release InformationModelSimModelSim DesignerTechnical Resource CenterModelSimModelSim DesignerVerification Newsletter |
Announcing the ModelSim 6.2 Series |
6.2 is here!Our standards-based, integrated solution will provide the necessary functionality to address the most complex issues faced by your design teams. The 6.2 series expands the advanced design and debug capabilities in ModelSim as well as delivering improved performance, capacity, support for new design and verification language features in SystemVerilog and numerous productivity and ease-of-use enhancements. Here are just some of the new capabilities that 6.2 includes. Please read the release notes as well as the documentation provided for complete information on the release. Highlights:
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Accelerating Test Bench Creation for Verilog and VHDL Designs Using MATLAB®, Simulink®, and Link for ModelSim® |
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Webinar presented by The MathworksDate: Thursday, July 13, 2006 Studies show that for every line of hardware description language (HDL) used to design digital hardware, engineers write five lines of test benches, also using HDL, despite the fact that HDLs are not ideal as "test bench description languages." Using traditional methods, writing the necessary test benches for a digital hardware design is very time consuming and siphons effort away from optimizing the design itself. In this webinar, we will demonstrate how engineers designing in Verilog or VHDL can write their test benches in a fraction of the time using MATLAB, Simulink, and ModelSim (from Mentor Graphics) via Link for ModelSim. In addition, if test benches originally created to validate the executable specification are available, you can reuse them for verification of the design, leading to further time saving and fewer errors. |
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DAC 2006Mentor Graphics at DAC Verification continues to be a major challenge with a plethora of tools, languages, and different verification platforms available to the customer. We will have multiple activities including booth demos, suite sessions, panels and more to highlight our Advanced Verification Solution and Methodology. Exploring the Landscape of Advanced Functional Verification Methodology DAC tutorialPresented by Doulos and Mentor Graphics This workshop will discuss functional verification methodologies as exemplified by Mentor Graphics' Advanced Verification Methodology (AVM). Assertion Based Verification, Coverage Driven Verification, Test Bench Automation, and Transaction Level Modeling will be introduced and positioned within the context of the verification flow. The workshop will illustrate how the underlying language mechanisms of SystemVerilog and SystemC get harnessed to create a unified verification methodology. SystemVerilog: Language Tutorial and Industrial Verification ExperienceFriday, July 28 This tutorial will provide a detailed overview of the IEEE 1800 SystemVerilog Hardware Design and Verification Language (HDVL), including practical examples of industrial experience using the language to develop complex designs. The tutorial will include a thorough description of the SystemVerilog definition, intent and potential while covering the design modeling, testbench automation, verification, assertions aspects of the language, and the programming interfaces. The practical sessions will include discussions of what has worked well, the impact on design and verification productivity and transition experiences from Verilog to SystemVerilog, as well as suggestions of possible future directions for the language. Efficient Multi-vendor Design and Verification flows - Proof that they exist!Technical Luncheon at DAC 2006! ARM and Mentor Graphics cordially invite you and your colleagues to attend a free technical seminar at DAC. ARM and Mentor will demonstrate an advanced system-optimization and verification solution that addresses an automated flow from SystemC platform development through fabric generation to full system assembly including complex, configurable IP to software creation and full system verification. Thursday, July 27th, Lunch will be provided. Space is limited, so register today. First 100 attendees will receive free gift and be included in drawing for mini-iPod to be given away at the conclusion of the seminar. Advanced Design Techniques for FPGAs online seminarPresented by Altera and Mentor Graphics With every new design, your challenge gets bigger. You're faced with creating a better solution in less time. This online seminar discusses the latest design features and devices for creating, debugging & simulating your next design, as well as explore advanced verification techniques to efficiently manage functionally verifying millions of gates. More information and Register! ModelSim TrainingTraining Opportunities Looking for training outside of North America? Search the world ModelSim HDL Simulation Advanced ModelSim Verilog Comprehensive |
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