The Hitchhiker's Guide to Verification
North America Seminar Tour
Having a very bad day? Your last chip required a respin, you just
realized that there's a whole class of bugs that your testbench just
isn't set up to catch, and to top things off, you don't have enough
verification engineers to write all the tests you're going to need.
DON'T PANIC!
Your only chance for survival: hitch a ride with a friendly team of
verification experts. With The Hitchhiker's Guide to Verification
seminar, you'll set out on a journey in which you'll find the secret to
Life, the Universe and Everything (or at least the secret to Testbench
Automation, Reuse, and Functional Coverage).
Set up mostly in two parallel tracks, the day will begin with an
introduction to Mentor Graphics' Advanced Verification Methodology
(AVM), which greatly facilitates the development of transaction-level
testbenches that can be used to verify designs at multiple levels of
abstraction.
2006 Dates and Location:
San Jose, CA – June 6th
Austin, TX – June 8th
Boston, MA – June 13th
Irvine, CA – June 15th
Toronto, Canada – June 20th
Ottawa, Canada – June 22nd
More Information and Register!
Improve Your Productivity with the
Right Verification Methodology Seminar
In this one-day seminar, you'll discover how the right verification
methodology is key to understanding and productivity between your
design, verification, software and systems teams. Our Verification
seminar will teach you everything you need to know to apply the latest
verification techniques to solve your most pressing problems.
Set up mostly in two parallel tracks, the day will begin with an
introduction to Mentor Graphics' Advanced Verification Methodology
(AVM), which greatly facilitates the development of transaction-level
testbenches that can be used to verify designs at multiple levels of
abstraction. After that, we break into two more-focused tracks.
Date and Location:
June 30th, 2006 – Bangalore, India
More information and Register
Partitioning and Synthesizing ASIC
Prototypes Using FPGAs
Online - June 7 at 11:00 am PDT
If you are designing an ASIC, a re-spin due to verification errors can
result in millions of dollars in cost and schedule overruns. More and
more ASIC designers consider prototyping in FPGAs as a way to reduce
risk and verify design functionality before committing to silicon. Using
Altera FPGAs and Mentor Graphics synthesis tools, you can now fully
realize the promised benefits of prototyping and thus ensure that your
ASIC designs will work as intended, on time and within budget!
More information and registration
Achieving Timing Closure in FPGAs with
Precision Synthesis: Hands-on Workshop
Start Designs Right, Improve Designs Faster, Meet Project Requirements
- Verifying timing constraints on
complex designs
- Identifying timing problems through
physical design analysis
- Addressing timing issues in the RTL
domain
- Addressing timing issues in the
physical domain
Locations and Dates:
San Jose, CA - June 8
El Segundo, CA - June 21
Submit your interest
Design Creation to Realization from
ModelSim Designer Seminars - France
This seminar will introduce, ModelSim Designer, a complete FPGA design
environment. Our focus is on improving your productivity which means the
complete process of creation, management, simulation, and implementation
is controlled from a single user interface, facilitating the design flow
and providing significant productivity gains. Single environment means a
shorter learning curve so you can realize your vision faster.
6/14 - Toulouse, FR
6/15 - Montpellier, FR
6/20 - Meudon-La-Forêt, FR
More information and Registration
ModelSimUConference
2006 France
Thursday, June 22, 2006 in Noget sur Marne (94)
Please register today and be entered to win an IPOD
Register before June 15:
phone : 01 60 20 11 11 (Isabelle)
email : info@cadinformatique.com
or Web :
www.cadinformatique.com/contactformMUG.htm
0-In Seminar
Jun 7, 2006 : Milan, IT
More information
and Registration
FPGA and PCB Update Seminar
Nel
corso del seminario verranno presentate le novitá introdotte con le
nuove release di quest'anno, in ambito FPGA (HDLdesigner, Precision,
Modelsim) e PCB (EE 2005.1).Durante la mattinata ci saranno due
sessioni parallele, una sessione dedicata alla progettazione FPGA,
l'altra focalizzata sul flusso PCB
Milan, Italy, June 15th
Technology Forum &
Technology Leadership Day,
Switzerland - June 20th
EDA
Tech Forum Provides Technical Resources for the Electronic Design
Community
In order to continue
innovating and succeeding, design engineers need a trusted resource for
information and analysis that helps them make the correct technology
decisions. The EDA Tech Forum provides this resource, bringing together
EDA industry experts, the EE design community and solution providers to
collectively address the hottest issues, trends and products that affect
the EDA industry.
More Information |
