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 Your Resource for Simulation Information March 30, 2006 


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Informant, a monthly newsletter that focuses on bringing you technical information on Simulation products from Mentor Graphics®. You can update your preferences at anytime at the Informant site. We welcome your feedback and hope you enjoy the material.
 

Spotlight

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  • VHDL, Verilog, and mixed-language graphic design entry management and simulation
  • Push-button support for the leading FPGA synthesis tools
  • Xilinx® Coregen Integration and support for ISE 7.1
  • Altera® MegaWizard Integration and support for Quartus II 5.0

More information and request a free 30-day evaluation

*Price shown in US dollars. Regional uplifts, exchange rates and taxes may apply.

 
ModelSim Designer Feature Demos   Standards Corner Mark Glasser
OSCI and The SPIRIT Consortium develop new standards

Last December IEEE approved the IEEE-1666 standard for SystemC. The IEEE-1666 LRM is now in the final stages of publication and will be released shortly. For updated information see the OSCI website.

The OSCI TLM working group is now working on a standard for model interoperability in SystemC. The TLM-1.0 standard, which was released last year, specifies channels and interfaces for connecting transaction level models. The new TLM interoperability standard will be based on the TLM-1.0 transport standard and will provide new standards for building bus channels and masters and slaves connected to the bus. The TLM-WG held a face-to-face meeting at DATE in Munich and is continuing its work with weekly meetings.

OSCI is in the process of forming a new working group to define standards for SystemC extensions to support analog and mixed signal designs. The formation of the SystemC-AMS working group is going through the final stages of approval. A study group has already formed and is beginning to work on requirements. You can find out more at the SystemC-AMS website.

The SPIRIT Consortium has completed the 1.2 version of the schema. It will be available on the SPIRIT Consortium’s website in mid-April.
 

Mark Glasser is a Verification Technologist in the Design Verification and Test division at Mentor Graphics.
 

Release Information
ModelSim Designer 6.1c ModelSim 6.1e
Technical Resource Center
ModelSim 6.1

Verification Newsletter


ESC 2006

Seamless and Seamless FPGA will be on exhibit at ESC 2006, being held in San Jose, April 4-7. Come see how these HW/SW integration tools detect and isolate HW/SW interface errors months ahead of hardware prototype. See Mentor tools in action at booth 1208.

More information


Design Creation to Realization from ModelSim Designer Seminar

This seminar will introduce, ModelSim Designer, a complete FPGA design environment. Our focus is on improving your productivity which means the complete process of creation, management, simulation, and implementation is controlled from a single user interface, facilitating the design flow and providing significant productivity gains. Single environment means a shorter learning curve so you can realize your vision faster.

Thursday April 6th, 2006 - Lyon, France

More information and registration


Japanese Technology Forum

Mentor Graphics will host a technology seminar, entitled "Leading Edge of IP Re-use," in Tokyo, Japan, on April 7th. This seminar will present an update on progress being made for specifications under development within The SPIRIT Consortium. It will also focus on user case-studies, with presentations from ARM and Philips Semiconductors, and introduce platform-based design methodologies based on Mentor's Platform Express tool.

7th April 2006
13:30-17:30 (Registration starts at 13:00)
Location: Mentor Graphics Japan Seminar Room; (4-7-35 Kita Shinagawa Gotenyama Garden 20 F)
Directions
Register

Please register by April 5. There is no charge for this seminar.


Seamless FPGA Workshop

San Jose, CA
April 12, 2006

More information


Get the Maximum Performance from ModelSim SE: Features & Performance Seminar

In this seminar, we will review the new and improved capabilities available in ModelSim. Topics to be covered include simulation performance (Volt Flow), new SystemVerilog language features for design, SystemC enhancements, managing simulation farms with JobSpy and debug and analysis capability improvements. We will also take a few minutes to review some existing ModelSim capabilities that many customers have found extremely valuable such as code coverage and innovative uses of VCD

Thursday April 13th, 2006 - San Jose, CA
Time: 11:30 – 1:30 (lunch included)

More information and registration


Improving Simulation Performance and Debugging of Designs

This session will discuss ModelSim as it continues to evolve as the new Standard Design and Verification languages are supported. Native support of Standard languages like SystemVerilog and SystemC add significant new functionality to the Simulation kernel and User interface. In addition, this seminar will also introduce ModelSim® Designer, the Windows®-based design environment for FPGAs.

Tuesday April 18th, 2006 - Dayton, OH
Time : 12:00 - 2:00 (Lunch included)

More Information and registration


Canada Design Forums

This is a technical conference covering sessions including Advanced FPGA Design, Coverage Driven Verification, Hardware/Software Co-verification and much more.

Tuesday April 25, 2006 - Montreal
Wednesday April 26, 2006 - Quebec

More Information and registration


Advanced Verification of VHDL Designs using SystemVerilog Seminar

This seminar is an introduction to advanced verification of VHDL designs using SystemVerilog with Questa from Mentor Graphics. This will include details on SystemVerilog constructs and how to integrate SystemVerilog Testbench Automation, Assertions Based Verification and Coverage Driven Verification with VHDL designs. Compatibilities that enable real users in the community to use the most advanced verification capabilities in the industry.

April 26th, 2006 - Tempe, Arizona
Time: 11:00 AM – 1:00 PM (lunch included)

More information and registration


ModelSim Local Europe User Conferences

This is a technical conference designed to help existing users of ModelSim gain more from their use of the tool, and to introduce you to the latest methodologies for the design and verification of complex ASIC and FPGA devices.

April 26th, 2006 - Newbury, UK
April 27th, 2006 - Frankfurt Germany


Mentor Graphics International User2User 2006

Mark your calendar for User2User 2006, May 2-5, in San Jose, CA.

User2User offers these exclusive benefits to Mentor Graphics customers:

  • 16 FREE hands-on, pre-conference workshops offered by Mentor engineers
  • Visit the Solution Center to see how the innovative features of the newest Mentor products can benefit your projects
  • A Microsoft Xbox executive keynote speaker will tell the story behind the wildly successful Xbox 360 and the future of gaming
  • 14 technical tracks will showcase 93 customer presentations, representing 75 companies from 12 countries, with real world examples
  • The Usability Lab enables attendees to give Mentor technical writers and product representatives direct feedback on product improvements
  • Discuss technical issues face to face with Mentor technical and product executives

Register now and see complete details


EDA Tech Forum® event series - 18 worldwide locations

In this no-cost, one-day forum you’ll:

  • Explore the future with industry expert keynotes
  • Test new products in hands on workshops
  • Delve into technology sessions covering:
    • Design for Manufacturability
    • Functional Verification
    • ESL
    • System Design

More information and register for a location near you


Training

Training Opportunities
Looking for training outside of North America? Search the world.

SystemVerilog, Design & Verification by Cliff Cummings
April 4, Phoenix
April 18, Marlboro

SystemVerilog with Questa
April 18, Dallas

ModelSim
April 11, San Jose

Advanced ModelSim
April 12, San Jose
 


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