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 Your Resource for Simulation Information February 27, 2006 


Welcome to the Informant, a monthly newsletter that focuses on bringing you technical information on Simulation products from Mentor Graphics®. You can update your preferences at anytime at the Informant site. We welcome your feedback and hope you enjoy the material.
 
Spotlight
ModelSim's Code Coverage Feature Provides Comprehensive Set of Metrics to Improve Your Verification Effort

The extensive analysis of your code allows you to find parts of the design that need further testing, and eliminate redundant tests, allowing faster and more effective regression suites. With ModelSim's powerful and easy-to-use graphical interface, you can easily identify untested code. Code Coverage is fully integrated into ModelSim's simulation kernel for best performance.

View a demo of Code Coverage.

Contact your sales representative for more information or go to www.model.com.
 
Release Information   Standards Corner Stephen Bailey
ModelSim Designer 6.1a ModelSim 6.1d OVL Supports PSL and SystemVerilog

 Accellera's Open Verification Library Technical Committee (OVL TC) has seen results from its new organizational structure. Formerly split into two semi-autonomous, the OVL TC has re-organized with one committee responsible for all versions of the assertion library.

Mike Turpin of ARM is the OVL TC Chair and he enjoys the support of Mentor Graphics' Kenneth Larsen as co-chair. The OVL TC has released a version of the OVL that fully supports the PSL (Property Specification Language, IEEE Std 1850) in Verilog and VHDL flavors. OVL is now implemented and supported for both PSL and SystemVerilog Assertions. As OVL was designed to work with simulation as well as formal verification, Questa and 0-in fully support OVL and the standard OVL source is provided in the latest product releases. They can also be downloaded from the Accellera website.

Stephen Bailey is the Vice Chair of the Accellera VHDL TC and the Product Marketing Manager for ModelSim at Mentor Graphics.
Technical Resource Center
ModelSim 6.1

Verification Newsletter
 Tri-Mode Processor Model for ARM Cores


For designs that incorporate or interface to an embedded CPU, processor driven tests can be a valuable addition to the suite of tests used to perform functional verification. Simply stated, processor drive tests, or PDT, are test vectors driven into the design via the processor bus and can originate from three sources. For a bus functional model these test consist of a sequence of reads and writes to desired register or memory locations serviced by the processor bus. In this mode, they resemble an HDL test bench where the bus functional model relieves the user of handling the complexity and detail of the bus protocol.

With a full functional model of the processor, tests in the form of embedded code are written in C or assembly and compiled to the target processor. These tests accurately replicate design function where the processor comes out of reset and begins fetching instructions which result in reads and writes to registers of peripherals, IP or custom logic.

A third method is to leverage the bus functional processor model to generate constrained random bus cycles. This mode is useful to load the bus with processor cycles while the ability for other bus masters to perform their data transfers is evaluated.

For more information, contact jim_kenney@mentor.com.
 
Altera and ModelSim Advanced Design Techniques for FPGAs Seminar

With every new design, your challenge gets bigger. You're faced with creating a better solution in half the time. Advanced design techniques & high performance devices can take you to the next level in FPGA design. Whether you're tackling thousands or millions of gates, you'll approach design from a whole new perspective. Learn how to apply advanced design techniques for creating, debugging & simulating your next design.

Thursday, March 16th
11:00 – 1:30 (lunch included)

Location:
Altera Corporation
101 Innovation Drive
Building #3
San Jose, CA 95134

Register today

Improving Simulation Performance and Debugging of Designs Seminar

This seminar will discuss ModelSim as it continues to evolve as the new Standard Design and Verification languages are supported. Native support of Standard languages like SystemVerilog and SystemC add significant new functionality to the Simulation kernel and User interface.

ModelSim delivers across the board with SystemVerilog for design support for more concise design descriptions to DPI capabilities and GUI enhancements that improve the analysis and debug of designs. In addition, this seminar will also introduce ModelSim® Designer, the Windows®-based design environment for FPGAs. It provides an easy to use, advanced-feature tool at an entry-level price. The complete process of creation, management, simulation, and implementation are controlled from a single user interface, facilitating the design and verification flow and providing significant productivity gains.

Seminar Dates and Locations:

  • March 6th – Minneapolis, MN
  • March 13th – Grand Rapids, MI
  • March 21st – Madison, WI
  • April 18th – Dayton, OH

Register today

Free Advanced Verification with Questa Seminar in Milan, Italy

The seminar will provide an understanding of relevant advanced verification topics utilizing SystemVerilog that will dramatically improve verifying today's complex SoC designs. You will learn the concepts and techniques behind an advanced verification methodology that can immediately be applied to your current projects.

March 15th

Register Now

DATE 2006

Once again, Mentor Graphics is sure to be the main attraction at the DATE-conference exhibition. With our wide range of best-in-class solutions, we have what you need for today's most challenging design problems. Come and see Mentor at booth A6.

March 7th - 9th

 More Info
 

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