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 Your Resource for Simulation Information January 31, 2006 


Welcome to the Informant, a monthly newsletter that focuses on bringing you technical information on Simulation products from Mentor Graphics®. You can update your preferences at anytime at the Informant site. We welcome your feedback and hope you enjoy the material.
 
Spotlight
ModelSim LE

Are you considering a Linux simulation farm for your next project? If so, please consider ModelSim LE.

ModelSim LE is an ideal product if you are looking for ModelSim's legendary ease-of-use and debug capabilities on the popular Linux platform at an aggressive price. ModelSim LE includes Waveform Compare and the enhanced Dataflow Window for easier debugging.

For more information, please contact your sales representative.
 
News
Mentor Recognized by IEEE

Dennis Brophy, director of strategic business development for the Design Verification and Test division at Mentor Graphics and Dave Rich, verification technologist for the Design Verification and Test division, have received the IEEE Working Group Chairman’s Award for their contributions to the IEEE SystemVerilog standard [more...]
 
 
Release Information   Standards Corner Dennis Brophy
ModelSim Designer 6.1a ModelSim 6.1d Accellera’s OVL Group Starts to Build PSL & VHDL Versions

 Accellera made some organizational changes to its OVL committee which delivered OVL 1.0 with SystemVerilog Assertion (SVA) and Verilog versions of the assertions. Mike Turpin from ARM is chair and Mentor’s Kenneth Larsen is co-chair of the reorganized group. The group has set a goal to complete OVL 2.0 by DAC 2006. OVL 2.0 will include VHDL and PSL versions of the popular checkers. The second major release of the Accellera Standard OVL will also enable users to take advantage of more advanced checking capabilities as well the control and reporting of individual checkers.

The OVL committee is actively looking for interested companies and individuals that are interested to help define the next versions of the Open Verification Library. The committee meets on a regular basis and has a bi-weekly conference call. If you are an employee of an Accellera member company and would like to join this group, click here to create your user account. If you are not an Accellera member and would like to join this group, click here to contact them.

Access to and use of the OVL 1.0 library, which includes the SVA and Verilog versions of the libraries today, is open to everyone free of charge. OVL has been tested to work with ModelSim and other Mentor Graphics verification products. Comprehensive documentation is also part of the package and we encourage its download.
 

Dennis Brophy is the Director of Strategic Business Development for the Design Verification and Test division at Mentor Graphics
Technical Resource Center
ModelSim 6.1

Verification Newsletter
DVCon, San Jose CA, February 22nd – 24th

Join us at DVCon by attending one of our multiple tutorials on Advanced Verification techniques, 6 technical sessions covering Verification Methodologies, Standards, SystemVerilog, System Level Design Productivity and much more.

In addition, on Thursday, join us for a special lunch presentation, Verification with SystemVerilog In Action: Leveraging the SystemVerilog Eco-System, with host Gabe Moretti, from Gabe on EDA & Mentor Graphics. This presentation will focus on verification with SystemVerilog to learn how SystemVerilog is leveraged to design state-of-the-art, leading-edge system-on-chips. You will learn more about the status of IEEE standardization along with short presentations from Mentor Graphics verification partners representing verification IP companies, verification consultancies and verification training companies that are deploying SystemVerilog language support in their product offerings today and all tested against Mentor Graphics' award winning implementation of SystemVerilog.

In the demo booth area, Mentor Graphics will feature Questa™ the advanced verification environment, 0-In® standards-based verification and functional coverage tools and Platform Express™, the Platform-based design and simulation environment that automates SoC assembly from RTL IP and Catapult C Synthesis for algorithmic synthesis.

More information

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