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 Your Resource for Simulation Information October 31, 2005 


Welcome to the Informant, a monthly newsletter that focuses on bringing you technical information on Simulation products from Mentor Graphics®. You can update your preferences at anytime at the Informant site. We welcome your feedback and hope you enjoy the material.
 
Spotlight
Mentor Graphics International User Conference

May 2-5, 2006 | San Jose, CA

Call For Papers Now Open! Abstract Submission Deadline: November 11, 2005

You are invited to share your technical expertise with other engineers and designers at User2User 2006. The primary goal of our highly-interactive, in-depth user conference is to deliver immediately useful technical knowledge.

Design engineers have shown an amazing ability to get designs working in spite of verification challenges. User papers describing verification insights, tool leverage, and successful strategies and methodologies of meeting this verification challenge are greatly welcomed. System, design, and test engineers are invited to share tool knowledge, best practices, verification language knowledge and experiences that are useful in overcoming the hurdles of verification.

Tell us about your design challenges, how you met them using Mentor Graphics tools, or where you needed to augment these tools to get your job done.

Complete abstract submission details.
Get the latest on Verification from Mentor Graphics

The advent of new technologies—such as constrained-random data generation, assertion-based verification, coverage-driven verification, and formal model checking—has changed the way we see functional verification productivity. Although simulation continues to be the heart of any realistic verification methodology, an advanced verification process enables users to manage the application of the aforementioned technologies in a complementary way, providing confidence that the myriad corner cases of today’s increasingly complex designs have been covered.  Therefore we have created a new newsletter to provide concepts, values, methodologies and examples to assist with the understanding of what these advanced functional verification technologies can do and how to most effectively apply them. 

As a ModelSim Informant reader, we invite you to register to receive the new quarterly Verification newsletter and monthly updates from Mentor Graphics.  You will continue to receive the Informant for the latest ModelSim news.

Register today!
 
Release Information   Standards Corner Stephen Bailey
ModelSim Designer 6.1a ModelSim 6.1 Questa Good News For Assertions

 The news is good for assertion based verification and the Property Specification Language (PSL). On 22 September 2005, IEEE's RevCom approved IEEE 1850, Standard for PSL Property Specification Language. The standard is now available for purchase from the IEEE.

Assertion-based verification mindshare has grown over the past year as reported in John Cooley's Verification Census on 25 October 2005. The popularity of PSL and SystemVerilog continues to grow. Mentor proudly supports both languages in full verification flows including simulation, formal verification and dynamic formal verification in the Questa and 0-in verification engines. Clearly, many engineers are discovering the benefits of greater debug productivity, higher design quality and better verification coverage knowledge that assertion-based verification brings.
 

Stephen Bailey is the Vice Chair of the Accellera VHDL TC and the Product Marketing Manager for ModelSim at Mentor Graphics.
Technical Resource Center
ModelSim 6.1

Questa

Questa Seminar Tour

This seminar will provide attendees with an understanding of relevant advanced verification topics that have been proven useful in verifying today's complex SoC designs. Concepts and techniques behind an advanced verification methodology that will be discussed include: Testbench Automation, Constrained-Random Verification, Assertions, Functional Coverage and Formal Verification.

Europe Dates and Locations

Solutions Expo 2005

We are pleased to invite you to this year's Solutions Expos in Europe.
As usual we have arranged an extensive and certainly interesting program for you.

Industry known speakers will talk about today's and tomorrow's technology challenges.
Dedicated conference tracks will focus on:

  • System and PCB design
  • FPGA- and Asic Design
  • Hot topics in Nanometer design
  • Scalable verification and test
  • Embedded Software development

In addition you will receive information at first hand as well as tips and tricks from users for users.

So don't miss this exciting opportunity to update your skills and technology knowledge, keeping you competitive in the global market.

Dates and locations

FPGA Update Seminar - News about Xilinx FPGAs and Mentor Graphics FPGA Tools

November 24th in Zürich. Switzerland

Mentor Graphics is pleased to invite you to the "FPGA Update" Seminar in Zurich. The seminar will address most recent news about Xilinx device families and the challenges Designers face in the development of today's FPGAs. Besides providing an overview about state of the art methodologies, new and emerging trends (such as assertion based verification, testbench automation, etc) will be covered as well.

Half- and/or Full Day In depth Technical Seminar: SystemVerilog – Advanced Verification with Questa

November 9th in Kobenhavn, Denmark

This seminar will provide attendees with an understanding of relevant advanced verification topics that have been proven useful in verifying today's complex mixed language SoC designs, and how to use SystemVerilog to apply them in practical ways on your current and future VHDL or Verilog projects.

Avoid Costly ASIC Respins! Using FPGAs for Prototyping

If you're designing an ASIC, a respin due to verification errors could mean millions of dollars in cost and schedule overruns. More and more ASIC designers consider prototyping in FPGAs as a way to reduce risk and verify design functionality before committing to silicon. Using Altera FPGAs and Mentor Graphics synthesis tools, you can now fully realize the promised benefits of prototyping and thus ensure that your ASIC designs will work as intended!

Register today for this two-hour Lunch and Learn Seminar

Lunch & Learn: Effective Verification on Freescale Secure Communications Processors

  • Discuss key technical benefits of the Freescale MPC8548E architecture
  • Verify hardware using a fully functional PowerQUICC model with an integrated debugger
  • Validate software before the hardware prototype is available
  • Utilize optimizations to improve simulation throughput
  • Reduce time in the integration lab once hardware is delivered

Waltham, MA - Nov. 10, 2005
San Jose, CA - Dec. 6, 2005

Register today

EDA Tech Forums

A one-day forum provides the EE design community the opportunity to network with peers. The format includes:

  • Industry expert keynotes
  • Hands-on workshop labs – you drive the tools
  • Vendor fair to discover the partners' latest solutions
  • Technical sessions in the following design areas:
    • System Design
    • Functional Verification
    • Embedded Systems Design
    • Design to Silicon
    • IC Nanometer Design
    • Electronic System Level Design

Events worldwide

Training

SystemVerilog Verification with Questa
Nov 10 Chicago

ModelSim HDL Simulation
Dec 13 San Jose

ModelSim Advanced Debugging
Dec 14 San Jose

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