Mid-Atlantic
Region Local Users Group
Thursday
Oct. 6th, 2005
John Hopkins University, Laurel, MD
Join us for 24 presentations across six tracks, a co-located vendor
fair, Mentor's own usability lab and a pre-show technical seminar on
October 5th on advanced verification with Mentor's new Questa product.
Register to
attend.
12th Annual Tcl/Tk
Conference
Come to the 12th Tcl/Tk
Conference to:
- Learn about the
power of Tcl/Tk.
- Present exciting
new work involving Tcl/Tk.
- See the latest
developments in Tcl/Tk.
- Meet Tcl/Tk
researchers and users from academia, government and industry.
- Plan for future
Tcl/Tk related developments.
The conference
program will include paper presentations, tutorials, Birds of a Feather
(BOF) sessions and invited key-note talks. The conference schedule will consist of 2 days of tutorials (Monday -
Tuesday) and 3 days for the main conference (Wednesday - Friday).
October 24th - 26th
Questa World Wide
Seminar Tour
This seminar will provide attendees with an understanding of relevant
advanced verification topics that have been proven useful in verifying
today's complex SoC designs. Concepts and techniques behind an advanced
verification methodology that will be discussed include: Testbench
Automation, Constrained-Random Verification, Assertions, Functional
Coverage and Formal Verification.
Europe Dates and Locations
Pacific Rim Dates and Locations
Japan Dates and Locations
ARM Developers’ Conference
The 2005 ARM Developers’ Conference will feature three days of in-depth
presentations from ARM, OEMs, Silicon Partners, EDA, and Tools and
Service Suppliers.
Visit the Mentor booth (#214) and attend our sessions.
October 4-6, 2005 – Santa Clara, CA
More
information
Solutions Expo 2005
We are pleased to invite you to this
year's Solutions Expos in Europe.
As usual we have arranged an extensive and certainly interesting program
for you.
Industry known speakers will talk about today's and tomorrow's
technology challenges.
Dedicated conference tracks will focus on:
- System and PCB design
- FPGA- and Asic Design
- Hot topics in Nanometer design
- Scalable verification and test
- Embedded Software development
In addition you will receive information
at first hand as well as tips and tricks from users for users.
So don't miss this exciting opportunity to update your skills and
technology knowledge, keeping you competitive in the global market.
Dates and locations
Workshop : FPGA
Re-spins Are No Longer Free
This workshop will demonstrate effectively how to meet complex design
requirements by analyzing performance and verifying functionality early
and frequently throughout the design process as well as address how to
identify pin assignment early on by synchronizing the HDL with the board
design.
Baltimore (Columbia) – October 5th
Chicago (Schaumburg) – November 3rd
Submit your interest today!
HDL
Design Seminars
Oct 11
in Zilina, Slovakia
Reduce Your HDL
Design Cycle by 30% Seminar
The challenge for designers today is to meet deadlines. Time savings can
be gained through improving techniques and having the right tools to
automate many of the tasks that would otherwise consume hours and even
weeks. Register to attend this lunch & learn seminar.
San Jose, October 11 and 25, November 8 and December 6
Registration
EDA Tech Forums
A one-day forum provides the EE design
community the opportunity to network with peers. The format includes:
- Industry expert keynotes
- Hands-on workshop labs – you drive
the tools
- Vendor fair to discover the
partners' latest solutions
- Technical sessions in the following
design areas:
- System Design
- Functional Verification
- Embedded Systems Design
- Design to Silicon
- IC Nanometer Design
- Electronic System Level Design
Events worldwide
Mentor Graphics
International User Conference
May 2-5, 2006 | San Jose, CA
Call For Papers Now Open! Abstract Submission Deadline: October 28, 2005
You are invited to share your technical expertise with other engineers
and designers at User2User 2006. The primary goal of our
highly-interactive, in-depth user conference is to deliver immediately
useful technical knowledge. We encourage you to submit an abstract for a
presentation that helps other Mentor users from around the world
understand your best practices, innovative design solutions, and success
stories.
Complete abstract
submission details.
ModelSim Training
SystemVerilog with Questa
Nov 1 Dallas
Nov 9 Austin
Nov 16 San Jose
ModelSim HDL Simulation
Nov 8 San Jose
ModelSim Advanced Debugging
Nov 9 San Jose |
ModelSim
has always been built around open standards from the initial embrace of
VHDL and the tool command language Tcl/Tk to today’s SystemVerilog,
SystemC and PSL languages now in the final stages of IEEE ratification.
ModelSim’s support of Tcl/Tk was a departure from company proprietary
schemes of the past, which made it easier for you and your design teams
to learn and use ModelSim to its fullest. Many of the tools in your
design chain followed our lead and are now using Tcl/Tk as well.