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 Your Resource for Design & Verification Information August 30, 2005 

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Spotlight
Advanced Verification with Questa North America seminar road show

This seminar will provide attendees with an understanding of relevant advanced verification topics that have been proven useful in verifying today's complex SoC designs, and how to use SystemVerilog to apply them in practical ways on your current and future projects. The morning session will provide an explanation of the concepts and techniques behind an advanced verification methodology, including:
  • Testbench Automation
  • Constrained-Random Verification
  • Assertions
  • Functional Coverage
  • Formal Verification

The afternoon session will show how to architect and assemble a testbench environment to deploy these verification techniques on illustrative examples. Examples will be shown using SystemVerilog, but additional material showing SystemC applications of the same techniques may be provided via follow-up discussions.

Whether you are starting from scratch on a new project, or are in the midst of a project in which you need to improve your verification methodology, this seminar will show you ways to get started today applying these powerful verification concepts with Questa. More information on dates & locations and to register
 
 
Release Information 
ModelSim 6.1

Questa

Technical Resource Center 
Standards Corner  Stephen Bailey
IEEE and Accellera collaborate on VHDL

When the Accellera Board met at DAC 2005, they approved the formation of a Technical Committee for VHDL (VHDL TC). The Accellera VHDL TC and IEEE 1076 Working Group (WG) have agreed on a process whereby Accellera will develop and refine enhancements to VHDL and the IEEE WG will provide fixes and clarifications for the existing LRM language and take the output from Accellera through IEEE standardization. The Accellera TC will leverage enhancements work already completed by the IEEE WG.

The Accellera VHDL TC is deep into the identification and prioritization of language enhancement requirements and will be working to satisfy high priority requirements through timely development of language enhancements. The VHDL TC meetings are open to anyone who wishes to participate. More information on the Accellera VHDL TC can be found at: http://www.accellera.org/activities/vhdl. The VHDL TC aims to publish its first draft of enhancements within a year.

 Stephen Bailey is the Vice Chair of the Accellera VHDL TC and the Product Marketing Manager for ModelSim at Mentor Graphics

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MARLUG 2005

Make plans now to attend MARLUG, the largest and longest running Mentor Graphics Local Users Group Conference.

October 6th

2005 MAPLD International Conference

The 8th annual MAPLD International Conference will present papers on programmable logic devices and technologies, digital engineering, and related fields, for military and aerospace applications.

September 7th-9th

EDA Tech Forums

Events worldwide

Automating Design Documentation using HDL Designer Series

Useful documentation should be complete, yet concise and most of all, it should be accurate. Addressing these documentation attributes takes time. HDL Designer saves you time by fulfilling these documentation attributes while helping you to create documents and automating design reviews.

September 14th, 10AM Pacific Daylight Time

Concurrent Design Creation and Checking: Reduce the Downstream Pain

This online seminar will discuss how using an integrated specification and checking environment can detect violations for standard rule sets specified in the Reuse Methodology Manual 3.0, along with Altera and Xilinx rules. Come and learn how to incorporate design checking into your environment and how it can accelerate your designs for market.

September 21st, 10AM Eastern Daylight Time

ModelSim Training

ModelSim HDL Simulation
Sept 13, Columbia, MD

ModelSim Advanced Debugging
Sept 14, Columbia, MD

VHDL Expert Verification
Sept 13, Marlboro