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Resource for Design & Verification Information |
July 19, 2005 |
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Welcome to the Informant, a
monthly newsletter that
focuses on bringing you technical information on Verification
products from Mentor Graphics®. You can update your preferences at anytime at the
Informant site.
We welcome your feedback
and hope you enjoy the material.
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| Spotlight |
ModelSim 6.1 Web Seminar
Tuesday July 26th, 9:00 AM PST
ModelSim® is the leading mixed language simulator for electronic
design supporting Verilog, VHDL, SystemC and SystemVerilog. In this
seminar, we will review the new and improved capabilities available
in the 6.1 release of ModelSim. Topics to be covered include
simulation performance, new SystemVerilog language features for
design, SystemC enhancements, managing simulation farms with JobSpy
and debug and analysis capability improvements. We will also take a
few minutes to review some existing ModelSim capabilities that many
customers have found extremely valuable such as code coverage and
innovative uses of VCD.
More
information and to register
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Advanced Verification with Questa North America
Seminar Road Show
 Questa™ is the new line of verification products from Mentor Graphics
that offers built-in support for testbench automation,
coverage-driven verification (CDV), assertion-based verification (ABV),
and transaction-level modeling (TLM).
This seminar will provide attendees with an understanding of
relevant advanced verification topics that have been proven useful
in verifying today's complex SoC designs, and how to use
SystemVerilog to apply them in practical ways on your current and
future projects. The morning session will provide an explanation of
the concepts and techniques behind an advanced verification
methodology, including:
- Testbench Automation
- Constrained-Random Verification
- Assertions
- Functional Coverage
- Formal Verification
The afternoon session will show how to architect and assemble a
testbench environment to deploy these verification techniques on
illustrative examples. Examples will be shown using SystemVerilog,
but additional material showing SystemC applications of the same
techniques may be provided via follow-up discussions.
Whether you are starting from scratch on a new project, or are in
the midst of a project in which you need to improve your
verification methodology, this seminar will show you ways to get
started today applying these powerful verification concepts with
Questa.
More information on dates & locations and to register. |
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ModelSim 6.1
Questa
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Technical Resource Center
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| Standards
Corner
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Dennis Brophy |
Early
Access to OVL in SystemVerilog Assertion (SVA) Format
 In
March 2005, Mentor Graphics announced it had donated its SystemVerilog
Assertion (SVA) version of the Open Verification Library (OVL) to
Accellera. With this donation,
the Accellera
OVL-VSVA
(access requires membership)
technical subcommittee was chartered to define and deliver an Accellera
standard OVL library of assertion checkers to be used by design,
integration and verification engineers to check good/bad behavior in
simulation, emulation and formal verification in the IEEE Std.
1364™-1995 (Verilog-95) language and the emerging IEEE SystemVerilog
(P1800) standard.
Users who have complaint SystemVerilog implementations supporting the
new Assertion features along with those who still use classic Verilog
can benefit from this new library of checkers. And those who may have
been using older versions of the OVL library for Verilog will find many
bug fixes for the classic version.
With the committee’s rapid finalization of its work, the committee
submitted its technical work for the OVL v1.0 library to the Accellera
Board of Directors for final approval to become an official standard of
the organization. The technical work includes OVL libraries in Verilog
and SystemVerilog, a Library Reference Manual and a timing diagram
tutorial, which can be downloaded from the technical committee web site
of Accellera. Registration is required for early access. Accellera
member companies can
request a login which will be automatically generated. Individuals
who are not affiliated with Accellera member companies can also
request an
observer login to gain access to the same information.
Dennis
Brophy is the Director of Strategic Business Development
for the Scalable Verification division at Mentor Graphics |
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ModelSim 6.1 New
features seminar
ModelSim continues to evolve as the new
Standard Design and Verification languages are supported. Native support
of Standard languages like SystemVerilog and SystemC add significant new
functionality to the Simulation kernel and User interface. ModelSim 6.1
delivers across the board with SystemVerilog for design support for more
concise design descriptions to DPI capabilities and GUI enhancements
that improve the analysis and debug of designs.
This presentation will introduce the new features that are available to
ModelSim users
Jul 26, Tempe, AZ
EDA Tech Forums
Events worldwide
Advanced Verification with HDL Designer Series
Today's
FPGAs require hundreds of probes and weeks of work to debug in the
lab. Engineers who fully test and debug their functionality in
ModelSim get out of the lab quickly and reliably. In this webinar,
you will learn how to create advanced self-checking testbenches
using familiar Verilog and VHDL that will get you into, and out of,
the lab more quickly.
North American Time Zones
European Time Zones
August 17th
September 28th
ModelSim Training
VHDL Comprehensive
August 1, Marlboro
August 22, Columbia
SystemVerilog, Design & Verification
by Cliff Cummings
August 10, Marlboro
Verilog Comprehensive
August 16, San Jose
PSL: Assertion Based Verification with ModelSim
Aug 30, Marlboro |
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