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 Your Resource for Design & Verification Information June 28, 2005 


Welcome to the Informant, a monthly newsletter that focuses on bringing you technical information on Verification products from Mentor Graphics®. You can update your preferences at anytime at the Informant site. We welcome your feedback and hope you enjoy the material.
 
Spotlight
Introducing ModelSim 6.1

Productivity is the goal and ModelSim 6.1 delivers across the board from its SystemVerilog for design support for more concise design descriptions to DPI capabilities and GUI enhancements that improve the analysis and debug of designs. ModelSim provides a single-kernel architecture that gives you the performance to do the fastest and most efficient simulation.

Request your free evaluation today.
 
Release Information 
ModelSim 6.1 Questa
Technical Resource Center 
New ModelSim 6.1 Demo

 ModelSim 6.1 demo now online

New Questa Demo

View the Questa demo
 
Standards Corner  Stephen Bailey
Users & Accellera Drive VHDL Enhancement

Accellera, at its board of directors meeting at DAC, approved the formation of a VHDL Working Group (WG) at the request of VHDL user companies Nokia, IBM and Rockwell Collins. The charter of the VHDL working group is to leverage the work of other Accellera working groups, specifically SystemVerilog and PSL, to bring advanced verification capabilities to the VHDL user community. Mentor Graphics is pleased to be supporting and participating in this activity. As with SystemVerilog and PSL, the results of this working group will be submitted to the IEEE for standardization. A web page with information on the Accellera VHDL WG will be available at www.accellera.org. If your company is interested in the future evolution of VHDL, contact Accellera to participate in this new WG.

 Stephen Bailey is the Product Marketing Manager for ModelSim at Mentor Graphics

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DSP Seminars

Mentor Graphics would like to invite you to attend Altera's Code:DSP seminars! Altera's Code: DSP video, image and signal processing solutions allow designers to implement the next-generation of FPGA-based system architectures that boost digital signal processing (DSP) performance and lower overall costs. Mentor will be supporting the event and participating in a panel discussion on developing FPGA Co-Processors using ‘C’ language & modeling tools.

Dates and locations:

June 29, Paris
June 30, Oxford 

More information on this seminar in Europe

We look forward to seeing you there!
 

ModelSim Designer Webcast

Archived Webcast: Increase Productivity with ModelSim Designer

ModelSim® Designer is a Windows®-based design environment for FPGAs that combines the industry-leading capabilities of ModelSim with built-in design creation capabilities. It provides easy to use, advanced-features at an entry-level price. This seminar introduces the latest features with examples of how to use them in your design environment today.

View webcast
 

ModelSim Training

SystemVerilog Design and Verification
by Cliff Cummings
July 19, San Jose
Aug 9, Marlboro

PSL: Assertion Based Verification with ModelSim
July 28, Marlboro

ModelSim HDL Simulation
July 25, Marlboro

ModelSim Advanced Topics
July 26, Marlboro