Verification Suite & Booth demonstrations
from Questa™, ModelSim® and 0-In®
Advances in
verification productivity are achieved through testbench automation
using constrained-random stimulus generation capabilities,
assertions to identify design flaws at or near the source of the
problem significantly reducing debug time while increasing design
quality. Coverage-driven verification delivers the predictability
needed to effectively manage the verification process by tracking
and reporting functional and code coverage for block and
system-level verification.
Come see these
latest solutions in action, seats are limited so
register today!
SystemVerilog for
Advanced Verification Methodology Discussion, Mentor Booth, #1800,
Tuesday 4:00 pm
Come to the Mentor
booth on Tuesday, June 14 , and join us for a brief discussion on
SystemVerilog and its importance as the leading standard for today's
complex verification challenges. Complimentary
beer and wine will be provided.
Accellera
SystemVerilog Booth, # 2284
Accellera has
taken Verilog to the next level of productivity and usefulness
through development of SystemVerilog, a set of extensions to the
Verilog language, to aid in the creation and verification of
abstract architectural level models. The SystemVerilog community of
suppliers will demonstrate products and services to showcase this
widely-supported language standard. Major EDA vendors will anchor
the booth and will give scheduled demonstrations during the exhibit
hours including a "Meet the Experts" discussion area. Come see a
demo of Mentor Graphics SystemVerilog solution for Assertions,
Functional Coverage and Constrained-random Testbenches.
Pavilion Panel, Did Assertions Help you C.Y.A. on your last design?
Thursday June 16th, 11:00 – 11:45, Booth # 2269
How
assertive can designers be when using assertions? Are assertions the
"holy grail" of verification? Do they significantly help reduce
design respins and improve first pass silicon success? Find out from
industry leaders how designers are using coverage-based
verification, and the benefits and results they have seen.
|
Moderator(s): |
David Maliniak - Electronic
Design Magazine, Paramus, NJ |
|
Speaker(s): |
Curt Widdoes - Mentor
Graphics Corp., San Jose, CA
Wolfgang Ecker - Infineon
Technologies, AG, Munich, Germany
Carey Kloss - Cisco Systems,
Inc., San Jose, CA |
Half day tutorial – Hot Core-Based SOC Design;
Design
of Multi-Core Systems with SystemC and Retargetable Processor Tools
(Target Compiler Technologies and ModelSim.)
This tutorial will
demonstrate how new ASIP cores can be designed and programmed
quickly, while at the same time ensuring the correctness of the
design, not only at the level of individual cores but also at the
overall system level.
In the hands-on
exercises, participants will design a small demo application,
including the following steps:
·
High-level SystemC
simulation of the overall application, using ModelSim.
·
Design and
programming of a few ASIP cores for some key functions of the
system, using the Chess/Checkers tools. This will include C
compilation onto these ASIP cores, as well as the automatic
generation of a cycle accurate instruction-set simulator (ISS) and
of a synthesizable Verilog model of each core.
·
Verification of
the architecture design, by integrating the generated ISSs in System
C and running co-simulation in ModelSim.
·
Verification of
the hardware, by integrating the generated Verilog models of the
ASIP cores in an RTL netlist of the total system, and simulating
everything in ModelSim.
Visit the
DAC site for more information and to register:
SystemC Symposium, Monday June 13th Room 304 A-B Anaheim
Convention Center 12:00 – 1:30 (Lunch Provided)
The
Open System C Initiative (OSCI) invites you to an industry symposium
to find out the compelling reasons for making the move up to
electronic system-level (ESL) design with SystemC. A panel of
experts will discuss the drivers for the move and how SystemC enables
the move, what adoption path they selected and evaluation of their
investment. [more
information]
With
the SystemVerilog standard nearing their completion in the IEEE,
Accellera has several DAC events and venues at which the value of this
work and future standards for verification will be discussed. New this
year is the Accellera SystemVerilog booth (#2284 near the food court).
Mentor Graphics is one of the anchor sponsors along with Cadence Design
Systems and Synopsys, to give the SystemVerilog community of suppliers a
single place to demonstrate products and services. The booth also
features a “Meet the Experts” discussion area. Accellera has invited the
design and verification community to come by the booth to see
SystemVerilog in action.