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 Your Resource for Design & Verification Information April 25, 2005 


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Spotlight
Productivity is the goal and ModelSim delivers across the board from its support for Assertion-Based verification, functional coverage, higher levels of abstraction and more concise design descriptions with SystemVerilog to GUI enhancements that improve the analysis and debug of designs. ModelSim provides a single-kernel architecture that gives you the performance to do the fastest and most efficient verification. Whether you are at the entry or advanced design level, ModelSim is your solution. Join us for one of our upcoming events.
Increase Productivity with ModelSim Designer - Webcast

ModelSim® Designer is a Windows®-based design environment for FPGAs that combines the industry-leading capabilities of ModelSim with built-in design creation capabilities. It provides easy to use, advanced-features at an entry-level price. The complete process of creation, management, simulation, and implementation are controlled from a single user interface with integrated FPGA vendor tool flow management features. ModelSim Designer provides significant productivity gains through automatic management of all your FPGA vendor generated files. This seminar introduces the latest features with examples of how to use them in your design environment today.
 
Webcast details:
  • Thursday, April 28, 2005
  • 8:00 AM PDT
 Register Now
Functional Verification with SystemVerilog Seminar

This seminar will discuss and show examples of Testbench Automation using SystemVerilog, Assertions Based Verification and Coverage Driven Verification to help you be more effective with your functional verification task
 
Two Colorado locations:
  • May 2, 2005 - Colorado Springs (11 am – 1 pm)
  • May 3, 2005 - Longmont (11 am – 1 pm)
 More details and registration information
Maximize Performance with ModelSim - Webcast

ModelSim continues to improve in Verilog RTL and Gate performance. There are also incremental improvements in VHDL RTL performance. ModelSim continues to be of the highest performance Simulators available. A new optional performance mode can automatically optimize Verilog and Mixed HDL designs. Learn the latest tips and techniques on how to maximize performance of your design and verification environment. This RTL and Gate flow discussion also includes Mixed HDL environments and how to use the new performance “vopt” mode.
 
Webcast details:
  • Thursday, April 28, 2005
  • 1:30 pm, PDT
 More details and registration information
Design Productivity through Applied Assertions and Testbench Automation Seminar

Join leading technologists from Mentor Graphics in a discussion on how to apply Assertions and Testbench Automation techniques to improve your time-to-market. Using industry standard SystemVerilog constructs and libraries, we will teach some of the techniques necessary to improve your design productivity and verification quality. The seminar will examine some of the testbench practices being successfully employed today as they become more widely available in standardized languages like SystemVerilog. It will explore how assertions can be used to more quickly reach verification closure while providing some “hands-on” experience in writing assertions. A methodology which applies state-of-the-art Formal Model Checking methods to further enhance the productivity of your design environment will be demonstrated. Join us for this free technical training and enjoy lunch on us!!!
 
Details:
  • June 2, 2005 - San Jose (11 am – 2 pm)
 More details and registration information
 
Release Information 
ModelSim 6.0
Support News
Answers to Technical Questions in SupportPro

Did you know that you can get more detailed information about practically any error or warning message from ModelSim by using the 'verror' command? This command was created in 5.6 release and has been improved upon in the latest [6.x] releases. You can learn how and when to use this command by reading Technote mg28444 in the SupportNet KnowledgeBase located here.

If you don't have a SupportNet login, and are a current support customer, signup for SupportNet and SupportPro technical newsletter by filling out this simple form .
 
Standards Corner 
IEEE Standardization of PSL
IEEE project P1850, Property Specification Language, is now being balloted. This will be the first IEEE version of PSL. This version of PSL enhances capabilities in many areas from Accellera's 1.1 version. Enhancements include additional HDL flavors for SystemC and SystemVerilog, addition of non-deterministic functions and resolution of many issues uncovered in the earlier versions of PSL. Mentor Graphics continues to support PSL through ModelSim and 0-in products.
 
Stephen Bailey, Product Marketing Manager, ModelSim

 
 
ModelSim Training 
ModelSim HDL Simulation

HDL Simulation with ModelSim teaches you to effectively use ModelSim to verify VHDL, Verilog, and mixed VHDL/Verilog designs. You will learn how ModelSim supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors.
May 24 Dallas

ModelSim Advanced Topics

ModelSim® Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim features and techniques and Debug Detective, you will learn how to produce higher performance models and higher performance and more reliable resultant designs. Hands-on lab exercises reinforce lecture and discussion topics and provide you with tool usage experience under the guidance of our industry expert instructors. You will be presented with real world design challenges and the tools and support to develop high quality test benches to stimulate and analyze designs under test and resolve these challenges in a methodical manner.
May 25 Dallas

Modeling & Verification in SystemC

This four-day class introduces the student to modeling and verification with C/C++ and the SystemC C++ class library including the SystemC Verification library (2.0-SCV). It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC with a modeling and verification focus. Version 2.0 and SystemC Verification Library concepts are taught.
More Details - Call 800-345-2308

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Assertion-Based Verification Seminar

Learn how ModelSim and 0-In standards based assertion engines and functional coverage will improve your verification productivity.

Apr 26  Vienna, Austria
Apr 27  Zürich, Switzerland
Apr 28  Madrid, Spain
May 10  Newbury, UK
May 19  Dublin, Ireland

Register now

EDA TechForum

Technical sessions covering the latest advances in:

- Emerging Technologies
- IC Nanometer Design
- Integrated System Design
- Functional Verification

Registration is now open for the following dates:

May 3rd  Dallas, TX
May 11th  Dresden, Germany
May 16th  Phoenix, AZ

 Register Today!

EDA Technical Road Show

Trilogic, in conjunction with Mentor Graphics is sponsoring a one day Electronic Design Automation Technical Road Show . This Road Show focuses on the latest technologies for the following products: Pads, DxDesigner, Hyperlynx, Expedition, ModelSim Designer, Design Analyst, and HDL Designer. Attend technical presentations or view a demo of the latest features.

May 12  Chelmsford, Massachusetts
May 17  Somerset, New Jersey
May 18  King of Prussia, Pennsylvania
May 19  Greenbelt, Maryland
June 1  Rochester, NY

Register to attend

Mentor Graphics Technology Forum

May 3  Göteborg, Sweden
May 10  Kolding, Denmark
May 11 København, Denmark
 

eScape to SystemVerilog Seminar

With strong interest in SystemVerilog for verification, many organizations that have been using the proprietary HVL e, are exploring a move to standards and SystemVerilog. This seminar provides guidance on transitioning to SystemVerilog for verification by showing and contrasting capabilities and common structures and techniques in both languages. This seminar will be valuable to Verisity®’s e users.

April 26  Tokyo, Japan
April 28  Beijing, China
May 16  Herzelyia, Israel
May 19  Eindhoven, Netherlands
May 20  Cambridge, UK
May 24  Sophia, France
May 25  Bristol, UK
May 26  Copenhagen, Denmark
May 31  Grenoble, France
June 1  Munich, Germany
June 2  Duesseldorf, Germany

Register Today!