Model.com | Register | Latest Release | Contact Us | Feedback 
 Your Resource for Design & Verification Information March 30, 2005 

Thank you for subscribing to ModelSim Informant, a service from the ModelSim® group at Mentor Graphics®. You can update your preferences at anytime at the ModelSim Informant site by specifying your email address and your password.
 
Spotlight
eScape To SystemVerilog Tour

With strong interest in SystemVerilog for verification, many organizations that have been using the proprietary HVL e, are exploring a move to standards and SystemVerilog. This seminar provides guidance on transitioning to SystemVerilog for verification by showing and contrasting capabilities and common structures and techniques in both languages. This seminar will be valuable to Verisity®’s e users.
Agenda highlights:
  • SystemVerilog Basics
  • Randomization and Constraints
  • Abstraction & Reuse
  • Functional Coverage
  • Inter-process Communication and Scoreboarding Assertions
  • Using  SystemVerilog Testbenches with VHDL Designs
 More information on dates,
locations and registration.

DesignAnalyst   Better, Faster, and Affordable…

Are you facing:
  • Tight Schedules for your ASIC/FPGA Design?
  • Inconsistent HDL coding from team members?
  • Challenges remembering best coding styles and guidelines?
 Do you need to :
  • Reduce Design Cycle Time?
  • Increase HDL Code Quality and Consistency?
  • Automate the Process of Checking?

The industry's first affordable desktop solution for High performance RTL static design checking. DesignAnlyst reduces design time and project cost by finding problems early while they can be fixed quickly and inexpensively.

Release Information 
ModelSim 6.0
Technical Resource Center
New Functional Verification White paper

Seamless FPGA Download

Developed in partnership with Xilinx for the Virtex-II Pro and Virtex-4, Seamless FPGA provides an enhanced PowerPC model which connects the XRAY software debugger with a hardware design running in ModelSim to speed design completion.
Standards Corner 
IEEE SystemVerilog Ballot Underway

The IEEE SystemVerilog Working Group has initiated a ballot of both the Verilog (P1364) and SystemVerilog (P1800) language reference manuals. The ballot closes in March with discussion and resolution of issues found by the ballot group the next few months. The ballot process is used to create consensus on these two standards and generally takes a few rounds of balloting to close. The IEEE process is one that address and circulates the negative issues found during ballot. Once there are no remaining negative ballots and all issues have been circulated within the ballot group, the proposed standards can then be sent to the IEEE Standards Association for certification and final approval to be IEEE standards. For P1364 and P1800 this means there is a good chance they will be ratified IEEE standards in 2005.
 
Dennis Brophy, Director of Strategic Business Development
The ModelSim team is engaged in driving changes and fixing issues with both Verilog and SystemVerilog in the IEEE. And the team is working to make sure newer versions of ModelSim track the consensus of the standards development team so ModelSim remains at the forefront of implementation and support for the advanced and new language features and constructs. Much of the proposed standards are available now and Informant readers will be kept current as additional elements are supported too

If you do not wish to receive future ModelSim Informant newsletters, update your subscription.  Or reply to this email message with "Opt out EMAIL" in the subject. Mentor Graphics 8005 SW Boeckman Road Wilsonville, OR, 97070, USA 800-547-3000 or 503-685-8000 Our privacy policy is also available.

Assertion-Based Verification Seminar

Learn how ModelSim and 0-In standards based assertion engines and functional coverage will improve your verification productivity.

Mar 31 Herzliya, Israel
Apr 5 Eindhoven, NL
Apr 13 Espoo, Finland
Apr 14 Tampere, Finland
Apr 15 Oulu, Finland
Apr 26 Vienna, Austria
Apr 27 Zürich, Switzerland
Apr 28 Madrid, Spain
May 10 Newbury, UK
May 19 Dublin, Ireland

Register now

EDA TechForum

Learn about the latest technology trends and challenges facing the EDA Design community. Focused discussions on Functional Verification

April 25th: Ottawa, ON
May 3rd: Dallas, TX 

Register Today!

Mentor Graphics User Conference

Join us for keynote speaker - Burt Rutan, designer of the first private manned spacecraft, 15 Verification presentations, demos of the latest ModelSim features and a special stage presentation by the MythBusters of Discovery Channel.

April 27 – 29, 2005
Santa Clara, CA

Register to attend

ModelSim Training

Expert Verilog Verification
 Austin, TX
April 12, 2005

ModelSim: HDL Simulation
 San Jose, CA
April 19, 2005
Dallas, TX
May 24, 2005

ModelSim Advanced Topics
San Jose, CA
April 20, 2005
Dallas, TX
May 25, 2005