ModelSim Informant - January 2005

Model.com | Register | Latest Release | Contact Us | Feedback

Your Resource for Design & Verification Information

February 28, 2005

Thank you for subscribing to ModelSim Informant, a service from the ModelSim® group at Mentor Graphics®. You can update your preferences at anytime at the ModelSim Informant site by specifying your email address and your password.

Spotlight - eScape To SystemVerilog

Interest in the use of SystemVerilog for verification is strong. Not surprisingly, many organizations that have lead the evolution in verification by using the proprietary HVL such as 'e', are exploring a move to standards and SystemVerilog. This seminar provides guidance on transitioning to SystemVerilog for verification by showing and contrasting language capabilities and how common verification structures and techniques are implemented in both languages. This seminar will be particularly valuable to those using Verisity®’s 'e' language.

Get practical and up-to-date guidance on transitioning to a standards-based verification methodology built on SystemVerilog.

Specific topics will include:

Language Basics
Randomization and Constraints
Abstraction & Reuse
Functional Coverage
Inter-process Communication and Scoreboarding
Assertions
Verification Environment Structure
Using SystemVerilog Testbenches with VHDL Designs

March 2nd 2005 - San Jose, CA
March 3rd 2005 - Dallas, TX
March 4th 2005 - Boston, MA

Additional locations and dates in North America, Europe, Israel, Japan and India coming soon.

Release Information

ModelSim 6.0

Technical Resource Center

New Assertions-based Verification Datasheet
Seamless FPGA delivers co-verification for Xilinx FPGAs with PowerPC processors, combining comprehensive hardware and software debug and analysis within an optimal iteration cycle. Watch a multimedia demo now.

Register today to gain unlimited access to our in-depth technical documents such as application notes, white papers, product documentation and release notes.

ModelSim in the News

How to Boost Verification Productivity (EE Design - January)
Debug Dilemma: Simulation or Emulate (FPGA Journal - January)
Special Report: SystemC (Electronic Design - January)
SystemVerilog Support (Electronic News - February)
eScape to SystemVerilog Seminars (Various - February)
eScape to SystemVerilog Seminars (EDA Confidential - February)
Simulation Savvy: Getting the Most from Your HDL (FPGA Journal - February)
Wally Rhines to Keynote DVCon 2005 (Yahoo - February)
DVCon - Keynote Delivered by Wally Rhines (EDN - February)
DVCon - Wally Rhines' Keynote (EE Times - February)
DVCon - Functional Verification (EE Times - February)
John Cooley's DVCon "Bigwigs" Panel (EE Design - February)
John Cooley Video on DVCon "Bigwigs" Panel (Deepchip.com - February)
Functional Verification Made Manageable" (EE Times "Design Currents," page 50, print format only - February 21)

SystemVerilog Seminar - Featuring Cliff Cummings

Milan, Italy
March 2, 2005
Espoo, Finland
March 3, 2005

eScape to SystemVerilog

San Jose, CA
March 2, 2005
Dallas, TX
March 3, 2005
Boston, MA
March 4, 2005

Assertions-Based Verification Seminar

Munich, Germany
March 16, 2005
Kista, Sweden
March 17, 2005
Livingstone, UK
March 18, 2005
Paris, France
March 22, 2005
Milan Italy
March 23, 2005
Herzliya, Israel
March 31, 2005

DATE

Munich, Germany
March 8, 2005

EDA TechForum

Long Beach, CA
March 16, 2005

ModelSim Training

ModelSim: HDL Simulation
San Jose, CA
March 8, 2005

ModelSim Advanced Debugging
San Jose, CA
March 9, 2005

PSL Assertion Based Verification with ModelSim
Irvine, CA
March 15, 2005