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 Your Resource for Design & Verification Information January 31, 2005 


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Spotlight - DVCon 2005
ModelSim @ DVCon, Booth #204
February 14-16, 2005 Double Tree Hotel San Jose, CA

The Power of Integrated Verification
Mentor will be demonstrating the power of integrated verification by applying assertion-based verification and coverage-driven verification within standards-based solutions.  Combining ModelSim, the only simulator supporting all standards, with 0-in, the leading assertions-based verification solution, delivers the power to verify the most challenging designs.

Register online for DVCon and stop by booth #204.

Learn more about our design & verification solutions by attending the following activities OR check out our website for more details.

  • We Love SystemVerilog - Cocktail Event

    SystemVerilog has generated a lot of interest in the design and verification community. It is a new standard that enables design and high-level verification in a single language. At the same time, it is based on an established language used for most designs today -- Verilog. The combination of the well-known and the new is why we love SystemVerilog.

Come and share in the possibilities that SystemVerilog offers and get all your questions answered. The fun begins at 5 PM on February 14th in the DVCon Exhibit Hall.
Release Information 
ModelSim 6.0
Technical Resource Center

Check out all the exciting offers ModelSim has to offer through our technical resource center.
Standards Corner 
Transitioning to SystemVerilog for Verification

In the past few years, Accellera initiated and completed the SystemVerilog standard that offers a single, comprehensive language to address both design and verification. Standards support is critical for sustainable design and verification reuse methodologies that allow you to protect your investment in designs, tools and verification flows.

Now that the IEEE is in the final stages of SystemVerilog ratification, it’s the right time to transition to SystemVerilog for verification. Mentor Graphics and our partners are working to make your transition to the unified design and verification language effortless. Numerous training companies worldwide offer education so you can get the maximum utilization out of SystemVerilog. Design and verification Intellectual Property (IP) companies are building qualified IP for you to use in SystemVerilog complaint tools. And, many of our value added partners are readying tools that will enhance our implementation of SystemVerilog.
Dennis Brophy, Director of Strategic Business Development
SystemVerilog offers you advanced design language constructs, direct interface to couple C/C++ code with Verilog code, fully integrated assertion mechanism and easy to use testbench automation features, which permits you to leverage advanced object-oriented programming techniques.

Mentor Graphics has been a leader in the Accellera and IEEE working groups to craft the best standard. As we collaborate with SystemVerilog adopters to offer you choices, we give you a simulation-centric verification environment built on standards to improve your design and verification efficiency. We invite you to come to DVCon and visit us at our booth #204 to see how we can help you transition to SystemVerilog for Verification and to learn why the time to transition is now.
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Power of SystemVerilog Seminar

San Jose, CA
February 10, 2005

DVCon

San Jose, CA
February 14-16, 2005

SystemVerilog Seminar - Featuring Cliff Cummings

Kista, Sweden
February 22, 2005

Oxford, UK
February 23, 2005

Munich, Germany
February 24, 2005

Herzliya, Israel
February 28, 2005

Milan, Italy
March 2, 2005

Espoo, Finland
March 3, 2005

EDA Tech Forum

Long Beach, CA
March 16, 2005

ModelSim Training

NEW! SystemVerilog NOW

Phoenix, AZ
February 8, 2005

ModelSim HDL Simulation

San Jose, CA
February 8, 2005

ModelSim Advanced Debugging

San Jose, CA
February 9, 2005

PSL Assertion Based Verification with ModelSim

Irvine, CA
March 15, 2005