Course Description
This ½ day hands-on workshop is designed to help engineers become familiar with the new Virtex-5 PCI Express Block from Xilinx. The presentation will cover PCIe basics, Xilinx PCIe Endpoint Block Plus v1.4 LogiCORE, Model Sim overview/tool enhancements, PCIe simulation and customizing the core. The labs will utilize the Xilinx CoreGen and ISE tools and be downloaded to the Xilinx ML555 Development kit.
Agenda:
- Overview
- Lab: Implementing the PCI Express Endpoint Block Plus v1.4 LogiCORE
- ModelSim: Overview & 6.3 Tools Update
- Lab: Simulating with the PCI Express Endpoint Block
- Lab: Installing and Running the Memory Endpoint Test (MET) Application
- Mentor: Hyperlynx – Signal Integrity
Location:
More information and to register. |
